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drm/i915/tgl: Updated Private PAT programming 

Gen12 removes the target-cache and age fields from the private PAT
because MOCS now have the capability to set these itself. Only memory-type
field should be programmed in the ppat, the reminded bits are reserved.

Since now there are only 4 possible combinations, we could set only 4
PPAT and leave the reminded 4 as UC, but I left them as WB as we used
to have before.

Also these registers have been relocated to the 0x4800-0x481c range.

HSDES: 1406402661
BSpec: 31654
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190817093902.2171-33-lucas.demarchi@intel.com
This commit is contained in:
Michel Thierry 2019-08-17 02:38:54 -07:00 committed by Chris Wilson
parent 13e53c5c53
commit b41e63d881
2 changed files with 17 additions and 1 deletions
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17
drivers/gpu/drm/i915/i915_gem_gtt.c
View File

@ -2862,6 +2862,19 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
return 0;
}
static void tgl_setup_private_ppat(struct drm_i915_private *dev_priv)
{
/* TGL doesn't support LLC or AGE settings */
I915_WRITE(GEN12_PAT_INDEX(0), GEN8_PPAT_WB);
I915_WRITE(GEN12_PAT_INDEX(1), GEN8_PPAT_WC);
I915_WRITE(GEN12_PAT_INDEX(2), GEN8_PPAT_WT);
I915_WRITE(GEN12_PAT_INDEX(3), GEN8_PPAT_UC);
I915_WRITE(GEN12_PAT_INDEX(4), GEN8_PPAT_WB);
I915_WRITE(GEN12_PAT_INDEX(5), GEN8_PPAT_WB);
I915_WRITE(GEN12_PAT_INDEX(6), GEN8_PPAT_WB);
I915_WRITE(GEN12_PAT_INDEX(7), GEN8_PPAT_WB);
}
static void cnl_setup_private_ppat(struct drm_i915_private *dev_priv)
{
I915_WRITE(GEN10_PAT_INDEX(0), GEN8_PPAT_WB | GEN8_PPAT_LLC);
@ -2942,7 +2955,9 @@ static void setup_private_pat(struct drm_i915_private *dev_priv)
{
GEM_BUG_ON(INTEL_GEN(dev_priv) < 8);
if (INTEL_GEN(dev_priv) >= 10)
if (INTEL_GEN(dev_priv) >= 12)
tgl_setup_private_ppat(dev_priv);
else if (INTEL_GEN(dev_priv) >= 10)
cnl_setup_private_ppat(dev_priv);
else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
chv_setup_private_ppat(dev_priv);

1
drivers/gpu/drm/i915/i915_reg.h
View File

@ -2456,6 +2456,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0)
#define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4)
#define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index) * 4)
#define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
#define BSD_HWS_PGA_GEN7 _MMIO(0x04180)
#define BLT_HWS_PGA_GEN7 _MMIO(0x04280)
#define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380)