ARM: mvebu: define crypto SRAM ranges for all armada-370 boards
Define the crypto SRAM ranges so that the resources referenced by the sa-sram node can be properly extracted from the DT. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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@ -74,7 +74,8 @@
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soc {
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
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MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
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MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
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internal-regs {
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internal-regs {
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serial@12000 {
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serial@12000 {
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@ -69,7 +69,8 @@
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soc {
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
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MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
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MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
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MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
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pcie-controller {
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pcie-controller {
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status = "okay";
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status = "okay";
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@ -61,7 +61,8 @@
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soc {
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
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MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
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MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
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MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
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pcie-controller {
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pcie-controller {
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status = "okay";
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status = "okay";
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@ -138,6 +139,10 @@
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phy-mode = "rgmii-id";
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phy-mode = "rgmii-id";
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};
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};
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crypto@90000 {
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status = "okay";
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};
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mvsdio@d4000 {
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mvsdio@d4000 {
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pinctrl-0 = <&sdio_pins3>;
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pinctrl-0 = <&sdio_pins3>;
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pinctrl-names = "default";
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pinctrl-names = "default";
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@ -63,7 +63,8 @@
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soc {
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
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MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
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MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
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MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
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pcie-controller {
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pcie-controller {
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status = "okay";
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status = "okay";
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@ -63,7 +63,8 @@
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soc {
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
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MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
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MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
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MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
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pcie-controller {
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pcie-controller {
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status = "okay";
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status = "okay";
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@ -74,7 +74,8 @@
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soc {
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
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MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
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MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
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pcie-controller {
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pcie-controller {
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status = "okay";
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status = "okay";
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@ -77,7 +77,8 @@
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soc {
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
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MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
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MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
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internal-regs {
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internal-regs {
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