iommu/arm-smmu: Fix event queues synchronization
SMMUv3 only sends interrupts for event queues (EVTQ and PRIQ) when they
transition from empty to non-empty. At the moment, if the SMMU adds new
items to a queue before the event thread finished consuming a previous
batch, the driver ignores any new item. The queue is then stuck in
non-empty state and all subsequent events will be lost.
As an example, consider the following flow, where (P, C) is the SMMU view
of producer/consumer indices, and (p, c) the driver view.
P C | p c
1. SMMU appends a PPR to the PRI queue, 1 0 | 0 0
sends an MSI
2. PRIQ handler is called. 1 0 | 1 0
3. SMMU appends a PPR to the PRI queue. 2 0 | 1 0
4. PRIQ thread removes the first element. 2 1 | 1 1
5. PRIQ thread believes that the queue is empty, goes into idle
indefinitely.
To avoid this, always synchronize the producer index and drain the queue
once before leaving an event handler. In order to prevent races on the
local producer index, move all event queue handling into the threads.
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Jean-Philippe Brucker
Will Deacon
parent
e2d42311ff
commit
b4163fb333
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@ -1161,36 +1161,66 @@ static irqreturn_t arm_smmu_evtq_thread(int irq, void *dev)
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struct arm_smmu_queue *q = &smmu->evtq.q;
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u64 evt[EVTQ_ENT_DWORDS];
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while (!queue_remove_raw(q, evt)) {
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u8 id = evt[0] >> EVTQ_0_ID_SHIFT & EVTQ_0_ID_MASK;
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do {
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while (!queue_remove_raw(q, evt)) {
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u8 id = evt[0] >> EVTQ_0_ID_SHIFT & EVTQ_0_ID_MASK;
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dev_info(smmu->dev, "event 0x%02x received:\n", id);
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for (i = 0; i < ARRAY_SIZE(evt); ++i)
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dev_info(smmu->dev, "\t0x%016llx\n",
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(unsigned long long)evt[i]);
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}
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dev_info(smmu->dev, "event 0x%02x received:\n", id);
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for (i = 0; i < ARRAY_SIZE(evt); ++i)
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dev_info(smmu->dev, "\t0x%016llx\n",
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(unsigned long long)evt[i]);
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}
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/*
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* Not much we can do on overflow, so scream and pretend we're
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* trying harder.
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*/
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if (queue_sync_prod(q) == -EOVERFLOW)
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dev_err(smmu->dev, "EVTQ overflow detected -- events lost\n");
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} while (!queue_empty(q));
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/* Sync our overflow flag, as we believe we're up to speed */
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q->cons = Q_OVF(q, q->prod) | Q_WRP(q, q->cons) | Q_IDX(q, q->cons);
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return IRQ_HANDLED;
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}
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static irqreturn_t arm_smmu_evtq_handler(int irq, void *dev)
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static void arm_smmu_handle_ppr(struct arm_smmu_device *smmu, u64 *evt)
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{
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irqreturn_t ret = IRQ_WAKE_THREAD;
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struct arm_smmu_device *smmu = dev;
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struct arm_smmu_queue *q = &smmu->evtq.q;
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u32 sid, ssid;
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u16 grpid;
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bool ssv, last;
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/*
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* Not much we can do on overflow, so scream and pretend we're
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* trying harder.
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*/
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if (queue_sync_prod(q) == -EOVERFLOW)
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dev_err(smmu->dev, "EVTQ overflow detected -- events lost\n");
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else if (queue_empty(q))
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ret = IRQ_NONE;
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sid = evt[0] >> PRIQ_0_SID_SHIFT & PRIQ_0_SID_MASK;
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ssv = evt[0] & PRIQ_0_SSID_V;
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ssid = ssv ? evt[0] >> PRIQ_0_SSID_SHIFT & PRIQ_0_SSID_MASK : 0;
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last = evt[0] & PRIQ_0_PRG_LAST;
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grpid = evt[1] >> PRIQ_1_PRG_IDX_SHIFT & PRIQ_1_PRG_IDX_MASK;
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return ret;
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dev_info(smmu->dev, "unexpected PRI request received:\n");
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dev_info(smmu->dev,
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"\tsid 0x%08x.0x%05x: [%u%s] %sprivileged %s%s%s access at iova 0x%016llx\n",
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sid, ssid, grpid, last ? "L" : "",
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evt[0] & PRIQ_0_PERM_PRIV ? "" : "un",
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evt[0] & PRIQ_0_PERM_READ ? "R" : "",
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evt[0] & PRIQ_0_PERM_WRITE ? "W" : "",
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evt[0] & PRIQ_0_PERM_EXEC ? "X" : "",
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evt[1] & PRIQ_1_ADDR_MASK << PRIQ_1_ADDR_SHIFT);
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if (last) {
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struct arm_smmu_cmdq_ent cmd = {
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.opcode = CMDQ_OP_PRI_RESP,
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.substream_valid = ssv,
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.pri = {
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.sid = sid,
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.ssid = ssid,
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.grpid = grpid,
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.resp = PRI_RESP_DENY,
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},
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};
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arm_smmu_cmdq_issue_cmd(smmu, &cmd);
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}
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}
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static irqreturn_t arm_smmu_priq_thread(int irq, void *dev)
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@ -1199,63 +1229,19 @@ static irqreturn_t arm_smmu_priq_thread(int irq, void *dev)
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struct arm_smmu_queue *q = &smmu->priq.q;
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u64 evt[PRIQ_ENT_DWORDS];
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while (!queue_remove_raw(q, evt)) {
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u32 sid, ssid;
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u16 grpid;
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bool ssv, last;
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do {
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while (!queue_remove_raw(q, evt))
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arm_smmu_handle_ppr(smmu, evt);
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sid = evt[0] >> PRIQ_0_SID_SHIFT & PRIQ_0_SID_MASK;
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ssv = evt[0] & PRIQ_0_SSID_V;
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ssid = ssv ? evt[0] >> PRIQ_0_SSID_SHIFT & PRIQ_0_SSID_MASK : 0;
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last = evt[0] & PRIQ_0_PRG_LAST;
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grpid = evt[1] >> PRIQ_1_PRG_IDX_SHIFT & PRIQ_1_PRG_IDX_MASK;
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dev_info(smmu->dev, "unexpected PRI request received:\n");
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dev_info(smmu->dev,
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"\tsid 0x%08x.0x%05x: [%u%s] %sprivileged %s%s%s access at iova 0x%016llx\n",
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sid, ssid, grpid, last ? "L" : "",
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evt[0] & PRIQ_0_PERM_PRIV ? "" : "un",
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evt[0] & PRIQ_0_PERM_READ ? "R" : "",
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evt[0] & PRIQ_0_PERM_WRITE ? "W" : "",
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evt[0] & PRIQ_0_PERM_EXEC ? "X" : "",
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evt[1] & PRIQ_1_ADDR_MASK << PRIQ_1_ADDR_SHIFT);
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if (last) {
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struct arm_smmu_cmdq_ent cmd = {
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.opcode = CMDQ_OP_PRI_RESP,
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.substream_valid = ssv,
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.pri = {
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.sid = sid,
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.ssid = ssid,
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.grpid = grpid,
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.resp = PRI_RESP_DENY,
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},
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};
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arm_smmu_cmdq_issue_cmd(smmu, &cmd);
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}
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}
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if (queue_sync_prod(q) == -EOVERFLOW)
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dev_err(smmu->dev, "PRIQ overflow detected -- requests lost\n");
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} while (!queue_empty(q));
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/* Sync our overflow flag, as we believe we're up to speed */
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q->cons = Q_OVF(q, q->prod) | Q_WRP(q, q->cons) | Q_IDX(q, q->cons);
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return IRQ_HANDLED;
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}
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static irqreturn_t arm_smmu_priq_handler(int irq, void *dev)
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{
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irqreturn_t ret = IRQ_WAKE_THREAD;
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struct arm_smmu_device *smmu = dev;
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struct arm_smmu_queue *q = &smmu->priq.q;
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/* PRIQ overflow indicates a programming error */
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if (queue_sync_prod(q) == -EOVERFLOW)
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dev_err(smmu->dev, "PRIQ overflow detected -- requests lost\n");
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else if (queue_empty(q))
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ret = IRQ_NONE;
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return ret;
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}
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static irqreturn_t arm_smmu_cmdq_sync_handler(int irq, void *dev)
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{
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/* We don't actually use CMD_SYNC interrupts for anything */
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@ -1288,15 +1274,11 @@ static irqreturn_t arm_smmu_gerror_handler(int irq, void *dev)
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if (active & GERROR_MSI_GERROR_ABT_ERR)
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dev_warn(smmu->dev, "GERROR MSI write aborted\n");
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if (active & GERROR_MSI_PRIQ_ABT_ERR) {
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if (active & GERROR_MSI_PRIQ_ABT_ERR)
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dev_warn(smmu->dev, "PRIQ MSI write aborted\n");
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arm_smmu_priq_handler(irq, smmu->dev);
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}
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if (active & GERROR_MSI_EVTQ_ABT_ERR) {
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if (active & GERROR_MSI_EVTQ_ABT_ERR)
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dev_warn(smmu->dev, "EVTQ MSI write aborted\n");
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arm_smmu_evtq_handler(irq, smmu->dev);
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}
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if (active & GERROR_MSI_CMDQ_ABT_ERR) {
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dev_warn(smmu->dev, "CMDQ MSI write aborted\n");
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@ -2235,10 +2217,10 @@ static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu)
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/* Request interrupt lines */
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irq = smmu->evtq.q.irq;
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if (irq) {
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ret = devm_request_threaded_irq(smmu->dev, irq,
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arm_smmu_evtq_handler,
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ret = devm_request_threaded_irq(smmu->dev, irq, NULL,
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arm_smmu_evtq_thread,
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0, "arm-smmu-v3-evtq", smmu);
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IRQF_ONESHOT,
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"arm-smmu-v3-evtq", smmu);
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if (ret < 0)
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dev_warn(smmu->dev, "failed to enable evtq irq\n");
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}
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@ -2263,10 +2245,10 @@ static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu)
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if (smmu->features & ARM_SMMU_FEAT_PRI) {
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irq = smmu->priq.q.irq;
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if (irq) {
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ret = devm_request_threaded_irq(smmu->dev, irq,
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arm_smmu_priq_handler,
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ret = devm_request_threaded_irq(smmu->dev, irq, NULL,
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arm_smmu_priq_thread,
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0, "arm-smmu-v3-priq",
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IRQF_ONESHOT,
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"arm-smmu-v3-priq",
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smmu);
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if (ret < 0)
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dev_warn(smmu->dev,
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