net: hns3: add support for Hisilicon ptp sync device

driver inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I78MGV
CVE: NA

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The hns3 driver provide ptp driver to get 1588 clock from
ethernet, but only the first PF on main chip can support this,
so, if getting ptp time from other chip, may have some bus
latency. The PTP sync device use to eliminate the bus latency.

Signed-off-by: Yonglong Liu <liuyonglong@huawei.com>
Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>

MAINTAINERS

@@ -9531,6 +9531,11 @@ S:	Maintained
 F:	Documentation/ABI/testing/debugfs-hisi-zip
 F:	drivers/crypto/hisilicon/zip/
 
+HISILICON HNS3 PTP SYNC DRIVER
+M:	Yonglong Liu <liuyonglong@huawei.com>
+S:	Supported
+F:	drivers/ptp/ptp_hisi.c
+
 HMM - Heterogeneous Memory Management
 M:	Jérôme Glisse <jglisse@redhat.com>
 L:	linux-mm@kvack.org

arch/arm64/configs/tencent.config

@@ -899,6 +899,7 @@ CONFIG_I2C_DESIGNWARE_PLATFORM=y
 CONFIG_I2C_XGENE_SLIMPRO=m
 CONFIG_I2C_SLAVE=y
 CONFIG_SPI=y
+CONFIG_PTP_HISI=m
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_DWAPB=y
 CONFIG_POWER_RESET_HISI=y

drivers/ptp/Kconfig

@@ -211,4 +211,15 @@ config PTP_DFL_TOD
 	  To compile this driver as a module, choose M here: the module
 	  will be called ptp_dfl_tod.
 
+config PTP_HISI
+	tristate "HiSilicon PTP sync platform driver"
+	help
+	  PTP sync driver work on multichip system, eliminates the bus latency
+	  between multichip, and provide a higher precision clock source. But
+	  the clock source of PTP sync device is from the RTC of HNS3 ethernet
+	  device, so, if you want the PTP sync device works, you must enable
+	  HNS3 driver also.
+
+	  If unsure, say N.
+
 endmenu

drivers/ptp/Makefile

@@ -20,3 +20,4 @@ obj-$(CONFIG_PTP_1588_CLOCK_MOCK)	+= ptp_mock.o
 obj-$(CONFIG_PTP_1588_CLOCK_VMW)	+= ptp_vmw.o
 obj-$(CONFIG_PTP_1588_CLOCK_OCP)	+= ptp_ocp.o
 obj-$(CONFIG_PTP_DFL_TOD)		+= ptp_dfl_tod.o
+obj-$(CONFIG_PTP_HISI)		+= ptp_hisi.o