clk: qcom: cpu-8996: simplify the cpu_clk_notifier_cb
- Do not use the Alt PLL completely. Switch to smux when necessary to prevent overvolting - Restore the parent in case the rate change aborts for some reason - Do not duplicate resetting the parent in set_parent operation. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-8-dmitry.baryshkov@linaro.org
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@ -506,27 +506,35 @@ static int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
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{
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struct clk_cpu_8996_pmux *cpuclk = to_clk_cpu_8996_pmux_nb(nb);
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struct clk_notifier_data *cnd = data;
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int ret;
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switch (event) {
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case PRE_RATE_CHANGE:
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ret = clk_cpu_8996_pmux_set_parent(&cpuclk->clkr.hw, ALT_INDEX);
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qcom_cpu_clk_msm8996_acd_init(base);
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/*
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* Avoid overvolting. clk_core_set_rate_nolock() walks from top
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* to bottom, so it will change the rate of the PLL before
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* chaging the parent of PMUX. This can result in pmux getting
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* clocked twice the expected rate.
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*
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* Manually switch to PLL/2 here.
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*/
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if (cnd->new_rate < DIV_2_THRESHOLD &&
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cnd->old_rate > DIV_2_THRESHOLD)
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clk_cpu_8996_pmux_set_parent(&cpuclk->clkr.hw, SMUX_INDEX);
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break;
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case POST_RATE_CHANGE:
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if (cnd->new_rate < DIV_2_THRESHOLD)
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ret = clk_cpu_8996_pmux_set_parent(&cpuclk->clkr.hw,
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SMUX_INDEX);
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else
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ret = clk_cpu_8996_pmux_set_parent(&cpuclk->clkr.hw,
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ACD_INDEX);
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case ABORT_RATE_CHANGE:
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/* Revert manual change */
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if (cnd->new_rate < DIV_2_THRESHOLD &&
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cnd->old_rate > DIV_2_THRESHOLD)
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clk_cpu_8996_pmux_set_parent(&cpuclk->clkr.hw, ACD_INDEX);
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break;
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default:
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ret = 0;
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break;
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}
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return notifier_from_errno(ret);
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return NOTIFY_OK;
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};
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static int qcom_cpu_clk_msm8996_driver_probe(struct platform_device *pdev)
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