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staging:r8188eu: remove NumTotalRFPath member of hal_data_8188e structure 

NumTotalRFPath is 1 for r8188eu chip.

Signed-off-by: Ivan Safonov <insafonov@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Ivan Safonov 2016-10-08 01:01:17 +07:00 committed by Greg Kroah-Hartman
parent 76fe8b32b4
commit b39db0b160
5 changed files with 49 additions and 106 deletions
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11
drivers/staging/rtl8188eu/hal/phy.c
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@ -278,7 +278,6 @@ void rtw_hal_set_bwmode(struct adapter *adapt, enum ht_channel_width bandwidth,
static void phy_sw_chnl_callback(struct adapter *adapt, u8 channel) static void phy_sw_chnl_callback(struct adapter *adapt, u8 channel)
{ {
u8 rf_path;
u32 param1, param2; u32 param1, param2;
struct hal_data_8188e *hal_data = adapt->HalData; struct hal_data_8188e *hal_data = adapt->HalData;
@ -286,12 +285,10 @@ static void phy_sw_chnl_callback(struct adapter *adapt, u8 channel)
param1 = RF_CHNLBW; param1 = RF_CHNLBW;
param2 = channel; param2 = channel;
for (rf_path = 0; rf_path < hal_data->NumTotalRFPath; rf_path++) { hal_data->RfRegChnlVal[0] = (hal_data->RfRegChnlVal[0] &
hal_data->RfRegChnlVal[rf_path] = (hal_data->RfRegChnlVal[rf_path] & 0xfffffc00) | param2;
0xfffffc00) | param2; phy_set_rf_reg(adapt, 0, param1,
phy_set_rf_reg(adapt, (enum rf_radio_path)rf_path, param1, bRFRegOffsetMask, hal_data->RfRegChnlVal[0]);
bRFRegOffsetMask, hal_data->RfRegChnlVal[rf_path]);
}
} }
void rtw_hal_set_chan(struct adapter *adapt, u8 channel) void rtw_hal_set_chan(struct adapter *adapt, u8 channel)

20
drivers/staging/rtl8188eu/hal/rf.c
View File

@ -137,17 +137,15 @@ static void getpowerbase88e(struct adapter *adapt, u8 *pwr_level_ofdm,
(powerbase0<<8) | powerbase0; (powerbase0<<8) | powerbase0;
*(ofdmbase+i) = powerbase0; *(ofdmbase+i) = powerbase0;
} }
for (i = 0; i < adapt->HalData->NumTotalRFPath; i++) { /* Check HT20 to HT40 diff */
/* Check HT20 to HT40 diff */ if (adapt->HalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
if (adapt->HalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20) powerlevel[0] = pwr_level_bw20[0];
powerlevel[i] = pwr_level_bw20[i]; else
else powerlevel[0] = pwr_level_bw40[0];
powerlevel[i] = pwr_level_bw40[i]; powerbase1 = powerlevel[0];
powerbase1 = powerlevel[i]; powerbase1 = (powerbase1<<24) | (powerbase1<<16) |
powerbase1 = (powerbase1<<24) | (powerbase1<<16) | (powerbase1<<8) | powerbase1;
(powerbase1<<8) | powerbase1; *mcs_base = powerbase1;
*(mcs_base+i) = powerbase1;
}
} }
static void get_rx_power_val_by_reg(struct adapter *adapt, u8 channel, static void get_rx_power_val_by_reg(struct adapter *adapt, u8 channel,
u8 index, u32 *powerbase0, u32 *powerbase1, u8 index, u32 *powerbase0, u32 *powerbase1,

70
drivers/staging/rtl8188eu/hal/rf_cfg.c
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@ -230,79 +230,33 @@ static bool rf6052_conf_para(struct adapter *adapt)
{ {
struct hal_data_8188e *hal_data = adapt->HalData; struct hal_data_8188e *hal_data = adapt->HalData;
u32 u4val = 0; u32 u4val = 0;
u8 rfpath;
bool rtstatus = true; bool rtstatus = true;
struct bb_reg_def *pphyreg; struct bb_reg_def *pphyreg;
for (rfpath = 0; rfpath < hal_data->NumTotalRFPath; rfpath++) { pphyreg = &hal_data->PHYRegDef[RF90_PATH_A];
pphyreg = &hal_data->PHYRegDef[rfpath]; u4val = phy_query_bb_reg(adapt, pphyreg->rfintfs, BRFSI_RFENV);
switch (rfpath) { phy_set_bb_reg(adapt, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
case RF90_PATH_A: udelay(1);
case RF90_PATH_C:
u4val = phy_query_bb_reg(adapt, pphyreg->rfintfs,
BRFSI_RFENV);
break;
case RF90_PATH_B:
case RF90_PATH_D:
u4val = phy_query_bb_reg(adapt, pphyreg->rfintfs,
BRFSI_RFENV << 16);
break;
}
phy_set_bb_reg(adapt, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1); phy_set_bb_reg(adapt, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
udelay(1); udelay(1);
phy_set_bb_reg(adapt, pphyreg->rfintfo, BRFSI_RFENV, 0x1); phy_set_bb_reg(adapt, pphyreg->rfHSSIPara2, B3WIREADDREAALENGTH, 0x0);
udelay(1); udelay(1);
phy_set_bb_reg(adapt, pphyreg->rfHSSIPara2, phy_set_bb_reg(adapt, pphyreg->rfHSSIPara2, B3WIREDATALENGTH, 0x0);
B3WIREADDREAALENGTH, 0x0); udelay(1);
udelay(1);
phy_set_bb_reg(adapt, pphyreg->rfHSSIPara2, rtstatus = rtl88e_phy_config_rf_with_headerfile(adapt);
B3WIREDATALENGTH, 0x0);
udelay(1);
switch (rfpath) { phy_set_bb_reg(adapt, pphyreg->rfintfs, BRFSI_RFENV, u4val);
case RF90_PATH_A:
rtstatus = rtl88e_phy_config_rf_with_headerfile(adapt);
break;
case RF90_PATH_B:
rtstatus = rtl88e_phy_config_rf_with_headerfile(adapt);
break;
case RF90_PATH_C:
break;
case RF90_PATH_D:
break;
}
switch (rfpath) {
case RF90_PATH_A:
case RF90_PATH_C:
phy_set_bb_reg(adapt, pphyreg->rfintfs,
BRFSI_RFENV, u4val);
break;
case RF90_PATH_B:
case RF90_PATH_D:
phy_set_bb_reg(adapt, pphyreg->rfintfs,
BRFSI_RFENV << 16, u4val);
break;
}
if (!rtstatus)
return false;
}
return rtstatus; return rtstatus;
} }
static bool rtl88e_phy_rf6052_config(struct adapter *adapt) static bool rtl88e_phy_rf6052_config(struct adapter *adapt)
{ {
struct hal_data_8188e *hal_data = adapt->HalData;
hal_data->NumTotalRFPath = 1;
return rf6052_conf_para(adapt); return rf6052_conf_para(adapt);
} }

51
drivers/staging/rtl8188eu/hal/rtl8188e_hal_init.c
View File

@ -135,7 +135,6 @@ void rtw_hal_read_chip_version(struct adapter *padapter)
dump_chip_info(ChipVersion); dump_chip_info(ChipVersion);
pHalData->VersionID = ChipVersion; pHalData->VersionID = ChipVersion;
pHalData->NumTotalRFPath = 1;
} }
void rtw_hal_set_odm_var(struct adapter *Adapter, enum hal_odm_variable eVariable, void *pValue1, bool bSet) void rtw_hal_set_odm_var(struct adapter *Adapter, enum hal_odm_variable eVariable, void *pValue1, bool bSet)
@ -470,7 +469,7 @@ void Hal_ReadTxPowerInfo88E(struct adapter *padapter, u8 *PROMContent, bool Auto
{ {
struct hal_data_8188e *pHalData = padapter->HalData; struct hal_data_8188e *pHalData = padapter->HalData;
struct txpowerinfo24g pwrInfo24G; struct txpowerinfo24g pwrInfo24G;
u8 rfPath, ch, group; u8 ch, group;
u8 bIn24G, TxCount; u8 bIn24G, TxCount;
Hal_ReadPowerValueFromPROM_8188E(&pwrInfo24G, PROMContent, AutoLoadFail); Hal_ReadPowerValueFromPROM_8188E(&pwrInfo24G, PROMContent, AutoLoadFail);
@ -478,34 +477,32 @@ void Hal_ReadTxPowerInfo88E(struct adapter *padapter, u8 *PROMContent, bool Auto
if (!AutoLoadFail) if (!AutoLoadFail)
pHalData->bTXPowerDataReadFromEEPORM = true; pHalData->bTXPowerDataReadFromEEPORM = true;
for (rfPath = 0; rfPath < pHalData->NumTotalRFPath; rfPath++) { for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) { bIn24G = Hal_GetChnlGroup88E(ch, &group);
bIn24G = Hal_GetChnlGroup88E(ch, &group); if (bIn24G) {
if (bIn24G) { pHalData->Index24G_CCK_Base[0][ch] = pwrInfo24G.IndexCCK_Base[0][group];
pHalData->Index24G_CCK_Base[rfPath][ch] = pwrInfo24G.IndexCCK_Base[rfPath][group]; if (ch == 14)
if (ch == 14) pHalData->Index24G_BW40_Base[0][ch] = pwrInfo24G.IndexBW40_Base[0][4];
pHalData->Index24G_BW40_Base[rfPath][ch] = pwrInfo24G.IndexBW40_Base[rfPath][4]; else
else pHalData->Index24G_BW40_Base[0][ch] = pwrInfo24G.IndexBW40_Base[0][group];
pHalData->Index24G_BW40_Base[rfPath][ch] = pwrInfo24G.IndexBW40_Base[rfPath][group];
}
if (bIn24G) {
DBG_88E("======= Path %d, Channel %d =======\n", rfPath, ch);
DBG_88E("Index24G_CCK_Base[%d][%d] = 0x%x\n", rfPath, ch , pHalData->Index24G_CCK_Base[rfPath][ch]);
DBG_88E("Index24G_BW40_Base[%d][%d] = 0x%x\n", rfPath, ch , pHalData->Index24G_BW40_Base[rfPath][ch]);
}
} }
for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) { if (bIn24G) {
pHalData->CCK_24G_Diff[rfPath][TxCount] = pwrInfo24G.CCK_Diff[rfPath][TxCount]; DBG_88E("======= Path %d, Channel %d =======\n", 0, ch);
pHalData->OFDM_24G_Diff[rfPath][TxCount] = pwrInfo24G.OFDM_Diff[rfPath][TxCount]; DBG_88E("Index24G_CCK_Base[%d][%d] = 0x%x\n", 0, ch , pHalData->Index24G_CCK_Base[0][ch]);
pHalData->BW20_24G_Diff[rfPath][TxCount] = pwrInfo24G.BW20_Diff[rfPath][TxCount]; DBG_88E("Index24G_BW40_Base[%d][%d] = 0x%x\n", 0, ch , pHalData->Index24G_BW40_Base[0][ch]);
pHalData->BW40_24G_Diff[rfPath][TxCount] = pwrInfo24G.BW40_Diff[rfPath][TxCount];
DBG_88E("======= TxCount %d =======\n", TxCount);
DBG_88E("CCK_24G_Diff[%d][%d] = %d\n", rfPath, TxCount, pHalData->CCK_24G_Diff[rfPath][TxCount]);
DBG_88E("OFDM_24G_Diff[%d][%d] = %d\n", rfPath, TxCount, pHalData->OFDM_24G_Diff[rfPath][TxCount]);
DBG_88E("BW20_24G_Diff[%d][%d] = %d\n", rfPath, TxCount, pHalData->BW20_24G_Diff[rfPath][TxCount]);
DBG_88E("BW40_24G_Diff[%d][%d] = %d\n", rfPath, TxCount, pHalData->BW40_24G_Diff[rfPath][TxCount]);
} }
} }
for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
pHalData->CCK_24G_Diff[0][TxCount] = pwrInfo24G.CCK_Diff[0][TxCount];
pHalData->OFDM_24G_Diff[0][TxCount] = pwrInfo24G.OFDM_Diff[0][TxCount];
pHalData->BW20_24G_Diff[0][TxCount] = pwrInfo24G.BW20_Diff[0][TxCount];
pHalData->BW40_24G_Diff[0][TxCount] = pwrInfo24G.BW40_Diff[0][TxCount];
DBG_88E("======= TxCount %d =======\n", TxCount);
DBG_88E("CCK_24G_Diff[%d][%d] = %d\n", 0, TxCount, pHalData->CCK_24G_Diff[0][TxCount]);
DBG_88E("OFDM_24G_Diff[%d][%d] = %d\n", 0, TxCount, pHalData->OFDM_24G_Diff[0][TxCount]);
DBG_88E("BW20_24G_Diff[%d][%d] = %d\n", 0, TxCount, pHalData->BW20_24G_Diff[0][TxCount]);
DBG_88E("BW40_24G_Diff[%d][%d] = %d\n", 0, TxCount, pHalData->BW40_24G_Diff[0][TxCount]);
}
/* 2010/10/19 MH Add Regulator recognize for CU. */ /* 2010/10/19 MH Add Regulator recognize for CU. */
if (!AutoLoadFail) { if (!AutoLoadFail) {

3
drivers/staging/rtl8188eu/include/rtl8188e_hal.h
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@ -200,9 +200,6 @@ struct hal_data_8188e {
u16 BasicRateSet; u16 BasicRateSet;
/* rf_ctrl */
u8 NumTotalRFPath;
u8 BoardType; u8 BoardType;
/* EEPROM setting. */ /* EEPROM setting. */