intel_idle: add core C6 optimization for SPR
commit 3a9cf77b60
upstream.
Add a Sapphire Rapids Xeon C6 optimization, similar to what we have for Sky Lake
Xeon: if package C6 is disabled, adjust C6 exit latency and target residency to
match core C6 values, instead of using the default package C6 values.
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Chen Zhuo <sagazchen@tencent.com>
Signed-off-by: Xinghui Li <korantli@tencent.com>
This commit is contained in:
parent
53e20e738f
commit
b39482cff5
|
@ -1526,6 +1526,8 @@ static void __init sklh_idle_state_table_update(void)
|
|||
*/
|
||||
static void __init spr_idle_state_table_update(void)
|
||||
{
|
||||
unsigned long long msr;
|
||||
|
||||
/* Check if user prefers C1E over C1. */
|
||||
if (preferred_states_mask & BIT(2)) {
|
||||
if (preferred_states_mask & BIT(1))
|
||||
|
@ -1539,6 +1541,19 @@ static void __init spr_idle_state_table_update(void)
|
|||
c1e_promotion_enable();
|
||||
disable_promotion_to_c1e = false;
|
||||
}
|
||||
|
||||
/*
|
||||
* By default, the C6 state assumes the worst-case scenario of package
|
||||
* C6. However, if PC6 is disabled, we update the numbers to match
|
||||
* core C6.
|
||||
*/
|
||||
rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr);
|
||||
|
||||
/* Limit value 2 and above allow for PC6. */
|
||||
if ((msr & 0x7) < 2) {
|
||||
spr_cstates[2].exit_latency = 190;
|
||||
spr_cstates[2].target_residency = 600;
|
||||
}
|
||||
}
|
||||
|
||||
static bool __init intel_idle_verify_cstate(unsigned int mwait_hint)
|
||||
|
|
Loading…
Reference in New Issue