[MTD] [NAND] Blackfin on-chip NAND Flash Controller driver
This is the driver for latest Blackfin on-chip nand flash controller - use nand_chip and mtd_info common nand driver interface - provide both PIO and dma operation - compiled with ezkit bf548 configuration - use hardware 1-bit ECC - tested with YAFFS2 and can mount YAFFS2 filesystem as rootfs ChangeLog from try#1 - use hweight32() instead of count_bits() - replace bf54x with bf5xx and BF54X with BF5XX - compare against plat->page_size in 2 cases when enable hardware ECC ChangeLog from try#2 - passed nand_test suites - use cpu_relax() instead of busy wait loop - some coding style issue pointed out by Andrew Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: David Woodhouse <dwmw2@infradead.org>
This commit is contained in:
Bryan Wu
David Woodhouse
parent
c4a9f88daf
commit
b37bde1478
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@ -91,6 +91,25 @@ config MTD_NAND_AU1550
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This enables the driver for the NAND flash controller on the
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AMD/Alchemy 1550 SOC.
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config MTD_NAND_BF5XX
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tristate "Blackfin on-chip NAND Flash Controller driver"
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depends on BF54x && MTD_NAND
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help
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This enables the Blackfin on-chip NAND flash controller
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No board specific support is done by this driver, each board
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must advertise a platform_device for the driver to attach.
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This driver can also be built as a module. If so, the module
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will be called bf5xx-nand.
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config MTD_NAND_BF5XX_HWECC
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bool "BF5XX NAND Hardware ECC"
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depends on MTD_NAND_BF5XX
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help
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Enable the use of the BF5XX's internal ECC generator when
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using NAND.
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config MTD_NAND_RTC_FROM4
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tristate "Renesas Flash ROM 4-slot interface board (FROM_BOARD4)"
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depends on SH_SOLUTION_ENGINE
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@ -13,6 +13,7 @@ obj-$(CONFIG_MTD_NAND_TOTO) += toto.o
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obj-$(CONFIG_MTD_NAND_AUTCPU12) += autcpu12.o
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obj-$(CONFIG_MTD_NAND_EDB7312) += edb7312.o
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obj-$(CONFIG_MTD_NAND_AU1550) += au1550nd.o
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obj-$(CONFIG_MTD_NAND_BF5XX) += bf5xx_nand.o
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obj-$(CONFIG_MTD_NAND_PPCHAMELEONEVB) += ppchameleonevb.o
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obj-$(CONFIG_MTD_NAND_S3C2410) += s3c2410.o
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obj-$(CONFIG_MTD_NAND_DISKONCHIP) += diskonchip.o
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@ -0,0 +1,788 @@
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/* linux/drivers/mtd/nand/bf5xx_nand.c
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*
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* Copyright 2006-2007 Analog Devices Inc.
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* http://blackfin.uclinux.org/
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* Bryan Wu <bryan.wu@analog.com>
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*
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* Blackfin BF5xx on-chip NAND flash controler driver
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*
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* Derived from drivers/mtd/nand/s3c2410.c
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* Copyright (c) 2007 Ben Dooks <ben@simtec.co.uk>
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*
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* Derived from drivers/mtd/nand/cafe.c
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* Copyright © 2006 Red Hat, Inc.
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* Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
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*
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* Changelog:
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* 12-Jun-2007 Bryan Wu: Initial version
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* 18-Jul-2007 Bryan Wu:
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* - ECC_HW and ECC_SW supported
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* - DMA supported in ECC_HW
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* - YAFFS tested as rootfs in both ECC_HW and ECC_SW
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*
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* TODO:
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* Enable JFFS2 over NAND as rootfs
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/ioport.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/bitops.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/nand_ecc.h>
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#include <linux/mtd/partitions.h>
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#include <asm/blackfin.h>
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#include <asm/dma.h>
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#include <asm/cacheflush.h>
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#include <asm/nand.h>
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#include <asm/portmux.h>
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#define DRV_NAME "bf5xx-nand"
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#define DRV_VERSION "1.2"
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#define DRV_AUTHOR "Bryan Wu <bryan.wu@analog.com>"
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#define DRV_DESC "BF5xx on-chip NAND FLash Controller Driver"
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#ifdef CONFIG_MTD_NAND_BF5XX_HWECC
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static int hardware_ecc = 1;
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#else
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static int hardware_ecc;
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#endif
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static unsigned short bfin_nfc_pin_req[] = {P_NAND_CE, P_NAND_RB, 0};
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/*
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* Data structures for bf5xx nand flash controller driver
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*/
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/* bf5xx nand info */
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struct bf5xx_nand_info {
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/* mtd info */
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struct nand_hw_control controller;
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struct mtd_info mtd;
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struct nand_chip chip;
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/* platform info */
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struct bf5xx_nand_platform *platform;
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/* device info */
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struct device *device;
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/* DMA stuff */
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struct completion dma_completion;
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};
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/*
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* Conversion functions
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*/
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static struct bf5xx_nand_info *mtd_to_nand_info(struct mtd_info *mtd)
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{
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return container_of(mtd, struct bf5xx_nand_info, mtd);
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}
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static struct bf5xx_nand_info *to_nand_info(struct platform_device *pdev)
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{
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return platform_get_drvdata(pdev);
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}
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static struct bf5xx_nand_platform *to_nand_plat(struct platform_device *pdev)
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{
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return pdev->dev.platform_data;
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}
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/*
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* struct nand_chip interface function pointers
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*/
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/*
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* bf5xx_nand_hwcontrol
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*
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* Issue command and address cycles to the chip
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*/
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static void bf5xx_nand_hwcontrol(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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if (cmd == NAND_CMD_NONE)
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return;
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while (bfin_read_NFC_STAT() & WB_FULL)
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cpu_relax();
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if (ctrl & NAND_CLE)
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bfin_write_NFC_CMD(cmd);
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else
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bfin_write_NFC_ADDR(cmd);
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SSYNC();
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}
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/*
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* bf5xx_nand_devready()
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*
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* returns 0 if the nand is busy, 1 if it is ready
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*/
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static int bf5xx_nand_devready(struct mtd_info *mtd)
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{
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unsigned short val = bfin_read_NFC_IRQSTAT();
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if ((val & NBUSYIRQ) == NBUSYIRQ)
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return 1;
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else
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return 0;
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}
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/*
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* ECC functions
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* These allow the bf5xx to use the controller's ECC
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* generator block to ECC the data as it passes through
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*/
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/*
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* ECC error correction function
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*/
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static int bf5xx_nand_correct_data_256(struct mtd_info *mtd, u_char *dat,
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u_char *read_ecc, u_char *calc_ecc)
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{
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struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
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u32 syndrome[5];
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u32 calced, stored;
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int i;
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unsigned short failing_bit, failing_byte;
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u_char data;
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calced = calc_ecc[0] | (calc_ecc[1] << 8) | (calc_ecc[2] << 16);
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stored = read_ecc[0] | (read_ecc[1] << 8) | (read_ecc[2] << 16);
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syndrome[0] = (calced ^ stored);
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/*
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* syndrome 0: all zero
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* No error in data
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* No action
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*/
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if (!syndrome[0] || !calced || !stored)
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return 0;
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/*
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* sysdrome 0: only one bit is one
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* ECC data was incorrect
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* No action
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*/
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if (hweight32(syndrome[0]) == 1) {
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dev_err(info->device, "ECC data was incorrect!\n");
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return 1;
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}
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syndrome[1] = (calced & 0x7FF) ^ (stored & 0x7FF);
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syndrome[2] = (calced & 0x7FF) ^ ((calced >> 11) & 0x7FF);
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syndrome[3] = (stored & 0x7FF) ^ ((stored >> 11) & 0x7FF);
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syndrome[4] = syndrome[2] ^ syndrome[3];
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for (i = 0; i < 5; i++)
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dev_info(info->device, "syndrome[%d] 0x%08x\n", i, syndrome[i]);
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dev_info(info->device,
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"calced[0x%08x], stored[0x%08x]\n",
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calced, stored);
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/*
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* sysdrome 0: exactly 11 bits are one, each parity
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* and parity' pair is 1 & 0 or 0 & 1.
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* 1-bit correctable error
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* Correct the error
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*/
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if (hweight32(syndrome[0]) == 11 && syndrome[4] == 0x7FF) {
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dev_info(info->device,
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"1-bit correctable error, correct it.\n");
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dev_info(info->device,
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"syndrome[1] 0x%08x\n", syndrome[1]);
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failing_bit = syndrome[1] & 0x7;
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failing_byte = syndrome[1] >> 0x3;
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data = *(dat + failing_byte);
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data = data ^ (0x1 << failing_bit);
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*(dat + failing_byte) = data;
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return 0;
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}
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/*
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* sysdrome 0: random data
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* More than 1-bit error, non-correctable error
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* Discard data, mark bad block
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*/
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dev_err(info->device,
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"More than 1-bit error, non-correctable error.\n");
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dev_err(info->device,
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"Please discard data, mark bad block\n");
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return 1;
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}
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static int bf5xx_nand_correct_data(struct mtd_info *mtd, u_char *dat,
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u_char *read_ecc, u_char *calc_ecc)
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{
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struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
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struct bf5xx_nand_platform *plat = info->platform;
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unsigned short page_size = (plat->page_size ? 512 : 256);
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int ret;
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ret = bf5xx_nand_correct_data_256(mtd, dat, read_ecc, calc_ecc);
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/* If page size is 512, correct second 256 bytes */
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if (page_size == 512) {
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dat += 256;
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read_ecc += 8;
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calc_ecc += 8;
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ret = bf5xx_nand_correct_data_256(mtd, dat, read_ecc, calc_ecc);
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}
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return ret;
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}
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static void bf5xx_nand_enable_hwecc(struct mtd_info *mtd, int mode)
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{
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return;
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}
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static int bf5xx_nand_calculate_ecc(struct mtd_info *mtd,
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const u_char *dat, u_char *ecc_code)
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{
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struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
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struct bf5xx_nand_platform *plat = info->platform;
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u16 page_size = (plat->page_size ? 512 : 256);
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u16 ecc0, ecc1;
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u32 code[2];
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u8 *p;
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int bytes = 3, i;
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/* first 4 bytes ECC code for 256 page size */
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ecc0 = bfin_read_NFC_ECC0();
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ecc1 = bfin_read_NFC_ECC1();
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code[0] = (ecc0 & 0x3FF) | ((ecc1 & 0x3FF) << 11);
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dev_dbg(info->device, "returning ecc 0x%08x\n", code[0]);
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/* second 4 bytes ECC code for 512 page size */
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if (page_size == 512) {
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ecc0 = bfin_read_NFC_ECC2();
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ecc1 = bfin_read_NFC_ECC3();
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code[1] = (ecc0 & 0x3FF) | ((ecc1 & 0x3FF) << 11);
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bytes = 6;
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dev_dbg(info->device, "returning ecc 0x%08x\n", code[1]);
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}
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p = (u8 *)code;
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for (i = 0; i < bytes; i++)
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ecc_code[i] = p[i];
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return 0;
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}
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/*
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* PIO mode for buffer writing and reading
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*/
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static void bf5xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
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{
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int i;
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unsigned short val;
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/*
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* Data reads are requested by first writing to NFC_DATA_RD
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* and then reading back from NFC_READ.
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*/
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for (i = 0; i < len; i++) {
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while (bfin_read_NFC_STAT() & WB_FULL)
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cpu_relax();
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/* Contents do not matter */
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bfin_write_NFC_DATA_RD(0x0000);
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SSYNC();
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while ((bfin_read_NFC_IRQSTAT() & RD_RDY) != RD_RDY)
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cpu_relax();
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buf[i] = bfin_read_NFC_READ();
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val = bfin_read_NFC_IRQSTAT();
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val |= RD_RDY;
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bfin_write_NFC_IRQSTAT(val);
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SSYNC();
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}
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}
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static uint8_t bf5xx_nand_read_byte(struct mtd_info *mtd)
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{
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uint8_t val;
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bf5xx_nand_read_buf(mtd, &val, 1);
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return val;
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}
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static void bf5xx_nand_write_buf(struct mtd_info *mtd,
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const uint8_t *buf, int len)
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{
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int i;
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for (i = 0; i < len; i++) {
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while (bfin_read_NFC_STAT() & WB_FULL)
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cpu_relax();
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bfin_write_NFC_DATA_WR(buf[i]);
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SSYNC();
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}
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}
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static void bf5xx_nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
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{
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int i;
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u16 *p = (u16 *) buf;
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len >>= 1;
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/*
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* Data reads are requested by first writing to NFC_DATA_RD
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* and then reading back from NFC_READ.
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*/
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bfin_write_NFC_DATA_RD(0x5555);
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SSYNC();
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for (i = 0; i < len; i++)
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p[i] = bfin_read_NFC_READ();
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}
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static void bf5xx_nand_write_buf16(struct mtd_info *mtd,
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const uint8_t *buf, int len)
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{
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int i;
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u16 *p = (u16 *) buf;
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len >>= 1;
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for (i = 0; i < len; i++)
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bfin_write_NFC_DATA_WR(p[i]);
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SSYNC();
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}
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/*
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* DMA functions for buffer writing and reading
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*/
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static irqreturn_t bf5xx_nand_dma_irq(int irq, void *dev_id)
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{
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struct bf5xx_nand_info *info = dev_id;
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clear_dma_irqstat(CH_NFC);
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disable_dma(CH_NFC);
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complete(&info->dma_completion);
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return IRQ_HANDLED;
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}
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static int bf5xx_nand_dma_rw(struct mtd_info *mtd,
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uint8_t *buf, int is_read)
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{
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struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
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struct bf5xx_nand_platform *plat = info->platform;
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unsigned short page_size = (plat->page_size ? 512 : 256);
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unsigned short val;
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dev_dbg(info->device, " mtd->%p, buf->%p, is_read %d\n",
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mtd, buf, is_read);
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/*
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* Before starting a dma transfer, be sure to invalidate/flush
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* the cache over the address range of your DMA buffer to
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* prevent cache coherency problems. Otherwise very subtle bugs
|
||||
* can be introduced to your driver.
|
||||
*/
|
||||
if (is_read)
|
||||
invalidate_dcache_range((unsigned int)buf,
|
||||
(unsigned int)(buf + page_size));
|
||||
else
|
||||
flush_dcache_range((unsigned int)buf,
|
||||
(unsigned int)(buf + page_size));
|
||||
|
||||
/*
|
||||
* This register must be written before each page is
|
||||
* transferred to generate the correct ECC register
|
||||
* values.
|
||||
*/
|
||||
bfin_write_NFC_RST(0x1);
|
||||
SSYNC();
|
||||
|
||||
disable_dma(CH_NFC);
|
||||
clear_dma_irqstat(CH_NFC);
|
||||
|
||||
/* setup DMA register with Blackfin DMA API */
|
||||
set_dma_config(CH_NFC, 0x0);
|
||||
set_dma_start_addr(CH_NFC, (unsigned long) buf);
|
||||
set_dma_x_count(CH_NFC, (page_size >> 2));
|
||||
set_dma_x_modify(CH_NFC, 4);
|
||||
|
||||
/* setup write or read operation */
|
||||
val = DI_EN | WDSIZE_32;
|
||||
if (is_read)
|
||||
val |= WNR;
|
||||
set_dma_config(CH_NFC, val);
|
||||
enable_dma(CH_NFC);
|
||||
|
||||
/* Start PAGE read/write operation */
|
||||
if (is_read)
|
||||
bfin_write_NFC_PGCTL(0x1);
|
||||
else
|
||||
bfin_write_NFC_PGCTL(0x2);
|
||||
wait_for_completion(&info->dma_completion);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void bf5xx_nand_dma_read_buf(struct mtd_info *mtd,
|
||||
uint8_t *buf, int len)
|
||||
{
|
||||
struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
|
||||
struct bf5xx_nand_platform *plat = info->platform;
|
||||
unsigned short page_size = (plat->page_size ? 512 : 256);
|
||||
|
||||
dev_dbg(info->device, "mtd->%p, buf->%p, int %d\n", mtd, buf, len);
|
||||
|
||||
if (len == page_size)
|
||||
bf5xx_nand_dma_rw(mtd, buf, 1);
|
||||
else
|
||||
bf5xx_nand_read_buf(mtd, buf, len);
|
||||
}
|
||||
|
||||
static void bf5xx_nand_dma_write_buf(struct mtd_info *mtd,
|
||||
const uint8_t *buf, int len)
|
||||
{
|
||||
struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
|
||||
struct bf5xx_nand_platform *plat = info->platform;
|
||||
unsigned short page_size = (plat->page_size ? 512 : 256);
|
||||
|
||||
dev_dbg(info->device, "mtd->%p, buf->%p, len %d\n", mtd, buf, len);
|
||||
|
||||
if (len == page_size)
|
||||
bf5xx_nand_dma_rw(mtd, (uint8_t *)buf, 0);
|
||||
else
|
||||
bf5xx_nand_write_buf(mtd, buf, len);
|
||||
}
|
||||
|
||||
/*
|
||||
* System initialization functions
|
||||
*/
|
||||
|
||||
static int bf5xx_nand_dma_init(struct bf5xx_nand_info *info)
|
||||
{
|
||||
int ret;
|
||||
unsigned short val;
|
||||
|
||||
/* Do not use dma */
|
||||
if (!hardware_ecc)
|
||||
return 0;
|
||||
|
||||
init_completion(&info->dma_completion);
|
||||
|
||||
/* Setup DMAC1 channel mux for NFC which shared with SDH */
|
||||
val = bfin_read_DMAC1_PERIMUX();
|
||||
val &= 0xFFFE;
|
||||
bfin_write_DMAC1_PERIMUX(val);
|
||||
SSYNC();
|
||||
|
||||
/* Request NFC DMA channel */
|
||||
ret = request_dma(CH_NFC, "BF5XX NFC driver");
|
||||
if (ret < 0) {
|
||||
dev_err(info->device, " unable to get DMA channel\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
set_dma_callback(CH_NFC, (void *) bf5xx_nand_dma_irq, (void *) info);
|
||||
|
||||
/* Turn off the DMA channel first */
|
||||
disable_dma(CH_NFC);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* BF5XX NFC hardware initialization
|
||||
* - pin mux setup
|
||||
* - clear interrupt status
|
||||
*/
|
||||
static int bf5xx_nand_hw_init(struct bf5xx_nand_info *info)
|
||||
{
|
||||
int err = 0;
|
||||
unsigned short val;
|
||||
struct bf5xx_nand_platform *plat = info->platform;
|
||||
|
||||
/* setup NFC_CTL register */
|
||||
dev_info(info->device,
|
||||
"page_size=%d, data_width=%d, wr_dly=%d, rd_dly=%d\n",
|
||||
(plat->page_size ? 512 : 256),
|
||||
(plat->data_width ? 16 : 8),
|
||||
plat->wr_dly, plat->rd_dly);
|
||||
|
||||
val = (plat->page_size << NFC_PG_SIZE_OFFSET) |
|
||||
(plat->data_width << NFC_NWIDTH_OFFSET) |
|
||||
(plat->rd_dly << NFC_RDDLY_OFFSET) |
|
||||
(plat->rd_dly << NFC_WRDLY_OFFSET);
|
||||
dev_dbg(info->device, "NFC_CTL is 0x%04x\n", val);
|
||||
|
||||
bfin_write_NFC_CTL(val);
|
||||
SSYNC();
|
||||
|
||||
/* clear interrupt status */
|
||||
bfin_write_NFC_IRQMASK(0x0);
|
||||
SSYNC();
|
||||
val = bfin_read_NFC_IRQSTAT();
|
||||
bfin_write_NFC_IRQSTAT(val);
|
||||
SSYNC();
|
||||
|
||||
if (peripheral_request_list(bfin_nfc_pin_req, DRV_NAME)) {
|
||||
printk(KERN_ERR DRV_NAME
|
||||
": Requesting Peripherals failed\n");
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
/* DMA initialization */
|
||||
if (bf5xx_nand_dma_init(info))
|
||||
err = -ENXIO;
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
/*
|
||||
* Device management interface
|
||||
*/
|
||||
static int bf5xx_nand_add_partition(struct bf5xx_nand_info *info)
|
||||
{
|
||||
struct mtd_info *mtd = &info->mtd;
|
||||
|
||||
#ifdef CONFIG_MTD_PARTITIONS
|
||||
struct mtd_partition *parts = info->platform->partitions;
|
||||
int nr = info->platform->nr_partitions;
|
||||
|
||||
return add_mtd_partitions(mtd, parts, nr);
|
||||
#else
|
||||
return add_mtd_device(mtd);
|
||||
#endif
|
||||
}
|
||||
|
||||
static int bf5xx_nand_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct bf5xx_nand_info *info = to_nand_info(pdev);
|
||||
struct mtd_info *mtd = NULL;
|
||||
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
|
||||
/* first thing we need to do is release all our mtds
|
||||
* and their partitions, then go through freeing the
|
||||
* resources used
|
||||
*/
|
||||
mtd = &info->mtd;
|
||||
if (mtd) {
|
||||
nand_release(mtd);
|
||||
kfree(mtd);
|
||||
}
|
||||
|
||||
peripheral_free_list(bfin_nfc_pin_req);
|
||||
|
||||
/* free the common resources */
|
||||
kfree(info);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* bf5xx_nand_probe
|
||||
*
|
||||
* called by device layer when it finds a device matching
|
||||
* one our driver can handled. This code checks to see if
|
||||
* it can allocate all necessary resources then calls the
|
||||
* nand layer to look for devices
|
||||
*/
|
||||
static int bf5xx_nand_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct bf5xx_nand_platform *plat = to_nand_plat(pdev);
|
||||
struct bf5xx_nand_info *info = NULL;
|
||||
struct nand_chip *chip = NULL;
|
||||
struct mtd_info *mtd = NULL;
|
||||
int err = 0;
|
||||
|
||||
dev_dbg(&pdev->dev, "(%p)\n", pdev);
|
||||
|
||||
if (!plat) {
|
||||
dev_err(&pdev->dev, "no platform specific information\n");
|
||||
goto exit_error;
|
||||
}
|
||||
|
||||
info = kzalloc(sizeof(*info), GFP_KERNEL);
|
||||
if (info == NULL) {
|
||||
dev_err(&pdev->dev, "no memory for flash info\n");
|
||||
err = -ENOMEM;
|
||||
goto exit_error;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, info);
|
||||
|
||||
spin_lock_init(&info->controller.lock);
|
||||
init_waitqueue_head(&info->controller.wq);
|
||||
|
||||
info->device = &pdev->dev;
|
||||
info->platform = plat;
|
||||
|
||||
/* initialise chip data struct */
|
||||
chip = &info->chip;
|
||||
|
||||
if (plat->data_width)
|
||||
chip->options |= NAND_BUSWIDTH_16;
|
||||
|
||||
chip->options |= NAND_CACHEPRG | NAND_SKIP_BBTSCAN;
|
||||
|
||||
chip->read_buf = (plat->data_width) ?
|
||||
bf5xx_nand_read_buf16 : bf5xx_nand_read_buf;
|
||||
chip->write_buf = (plat->data_width) ?
|
||||
bf5xx_nand_write_buf16 : bf5xx_nand_write_buf;
|
||||
|
||||
chip->read_byte = bf5xx_nand_read_byte;
|
||||
|
||||
chip->cmd_ctrl = bf5xx_nand_hwcontrol;
|
||||
chip->dev_ready = bf5xx_nand_devready;
|
||||
|
||||
chip->priv = &info->mtd;
|
||||
chip->controller = &info->controller;
|
||||
|
||||
chip->IO_ADDR_R = (void __iomem *) NFC_READ;
|
||||
chip->IO_ADDR_W = (void __iomem *) NFC_DATA_WR;
|
||||
|
||||
chip->chip_delay = 0;
|
||||
|
||||
/* initialise mtd info data struct */
|
||||
mtd = &info->mtd;
|
||||
mtd->priv = chip;
|
||||
mtd->owner = THIS_MODULE;
|
||||
|
||||
/* initialise the hardware */
|
||||
err = bf5xx_nand_hw_init(info);
|
||||
if (err != 0)
|
||||
goto exit_error;
|
||||
|
||||
/* setup hardware ECC data struct */
|
||||
if (hardware_ecc) {
|
||||
if (plat->page_size == NFC_PG_SIZE_256) {
|
||||
chip->ecc.bytes = 3;
|
||||
chip->ecc.size = 256;
|
||||
} else if (plat->page_size == NFC_PG_SIZE_512) {
|
||||
chip->ecc.bytes = 6;
|
||||
chip->ecc.size = 512;
|
||||
}
|
||||
|
||||
chip->read_buf = bf5xx_nand_dma_read_buf;
|
||||
chip->write_buf = bf5xx_nand_dma_write_buf;
|
||||
chip->ecc.calculate = bf5xx_nand_calculate_ecc;
|
||||
chip->ecc.correct = bf5xx_nand_correct_data;
|
||||
chip->ecc.mode = NAND_ECC_HW;
|
||||
chip->ecc.hwctl = bf5xx_nand_enable_hwecc;
|
||||
} else {
|
||||
chip->ecc.mode = NAND_ECC_SOFT;
|
||||
}
|
||||
|
||||
/* scan hardware nand chip and setup mtd info data struct */
|
||||
if (nand_scan(mtd, 1)) {
|
||||
err = -ENXIO;
|
||||
goto exit_error;
|
||||
}
|
||||
|
||||
/* add NAND partition */
|
||||
bf5xx_nand_add_partition(info);
|
||||
|
||||
dev_dbg(&pdev->dev, "initialised ok\n");
|
||||
return 0;
|
||||
|
||||
exit_error:
|
||||
bf5xx_nand_remove(pdev);
|
||||
|
||||
if (err == 0)
|
||||
err = -EINVAL;
|
||||
return err;
|
||||
}
|
||||
|
||||
/* PM Support */
|
||||
#ifdef CONFIG_PM
|
||||
|
||||
static int bf5xx_nand_suspend(struct platform_device *dev, pm_message_t pm)
|
||||
{
|
||||
struct bf5xx_nand_info *info = platform_get_drvdata(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bf5xx_nand_resume(struct platform_device *dev)
|
||||
{
|
||||
struct bf5xx_nand_info *info = platform_get_drvdata(dev);
|
||||
|
||||
if (info)
|
||||
bf5xx_nand_hw_init(info);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#else
|
||||
#define bf5xx_nand_suspend NULL
|
||||
#define bf5xx_nand_resume NULL
|
||||
#endif
|
||||
|
||||
/* driver device registration */
|
||||
static struct platform_driver bf5xx_nand_driver = {
|
||||
.probe = bf5xx_nand_probe,
|
||||
.remove = bf5xx_nand_remove,
|
||||
.suspend = bf5xx_nand_suspend,
|
||||
.resume = bf5xx_nand_resume,
|
||||
.driver = {
|
||||
.name = DRV_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init bf5xx_nand_init(void)
|
||||
{
|
||||
printk(KERN_INFO "%s, Version %s (c) 2007 Analog Devices, Inc.\n",
|
||||
DRV_DESC, DRV_VERSION);
|
||||
|
||||
return platform_driver_register(&bf5xx_nand_driver);
|
||||
}
|
||||
|
||||
static void __exit bf5xx_nand_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&bf5xx_nand_driver);
|
||||
}
|
||||
|
||||
module_init(bf5xx_nand_init);
|
||||
module_exit(bf5xx_nand_exit);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR(DRV_AUTHOR);
|
||||
MODULE_DESCRIPTION(DRV_DESC);
|
||||
|
|
@ -55,6 +55,7 @@
|
|||
#define CH_SPORT3_RX 20
|
||||
#define CH_SPORT3_TX 21
|
||||
#define CH_SDH 22
|
||||
#define CH_NFC 22
|
||||
#define CH_SPI2 23
|
||||
|
||||
#define CH_MEM_STREAM0_DEST 24
|
||||
|
|
|
|||
|
|
@ -0,0 +1,47 @@
|
|||
/* linux/include/asm-blackfin/nand.h
|
||||
*
|
||||
* Copyright (c) 2007 Analog Devices, Inc.
|
||||
* Bryan Wu <bryan.wu@analog.com>
|
||||
*
|
||||
* BF5XX - NAND flash controller platfrom_device info
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/* struct bf5xx_nand_platform
|
||||
*
|
||||
* define a interface between platfrom board specific code and
|
||||
* bf54x NFC driver.
|
||||
*
|
||||
* nr_partitions = number of partitions pointed to be partitoons (or zero)
|
||||
* partitions = mtd partition list
|
||||
*/
|
||||
|
||||
#define NFC_PG_SIZE_256 0
|
||||
#define NFC_PG_SIZE_512 1
|
||||
#define NFC_PG_SIZE_OFFSET 9
|
||||
|
||||
#define NFC_NWIDTH_8 0
|
||||
#define NFC_NWIDTH_16 1
|
||||
#define NFC_NWIDTH_OFFSET 8
|
||||
|
||||
#define NFC_RDDLY_OFFSET 4
|
||||
#define NFC_WRDLY_OFFSET 0
|
||||
|
||||
#define NFC_STAT_NBUSY 1
|
||||
|
||||
struct bf5xx_nand_platform {
|
||||
/* NAND chip information */
|
||||
unsigned short page_size;
|
||||
unsigned short data_width;
|
||||
|
||||
/* RD/WR strobe delay timing information, all times in SCLK cycles */
|
||||
unsigned short rd_dly;
|
||||
unsigned short wr_dly;
|
||||
|
||||
/* NAND MTD partition information */
|
||||
int nr_partitions;
|
||||
struct mtd_partition *partitions;
|
||||
};
|
||||
Loading…
Reference in New Issue