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drm/i915: fix gen2-gen3 backlight set 

Citing Jani's response to Imre's question in the review discussion:

> According to the gen2/3 bspec I have, the correct mask is
> BACKLIGHT_DUTY_CYCLE_MASK_PNV only in case of IS_PINEVIEW(dev), for
> everything else it's BACKLIGHT_DUTY_CYCLE_MASK.

What you say is correct, but we've treated all gen2/3 similar to PNV
since

commit ca88479c1c
Author: Keith Packard <keithp@keithp.com>
Date:   Fri Nov 18 11:09:24 2011 -0800

    drm/i915: Treat pre-gen4 backlight duty cycle value consistently

i.e. we only use the high 15 bits for all gen2/3. For non-PNV this just
means the lowest bit is always zero. For PNV the lowest bit has a
different meaning in both the PWM freq and duty cycle fields.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
[danvet: Make the commit message less empty.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Jani Nikula 2013-11-08 16:48:57 +02:00 committed by Daniel Vetter
parent 7bd688cd66
commit b329b32854
1 changed files with 7 additions and 3 deletions
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10
drivers/gpu/drm/i915/intel_panel.c
View File

@ -555,7 +555,7 @@ static void i9xx_set_backlight(struct intel_connector *connector, u32 level)
{
struct drm_device *dev = connector->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
u32 tmp;
u32 tmp, mask;
if (is_backlight_combination_mode(dev)) {
u32 max = intel_panel_get_max_backlight(connector);
@ -570,10 +570,14 @@ static void i9xx_set_backlight(struct intel_connector *connector, u32 level)
pci_write_config_byte(dev->pdev, PCI_LBPC, lbpc);
}
if (INTEL_INFO(dev)->gen < 4)
if (IS_GEN4(dev)) {
mask = BACKLIGHT_DUTY_CYCLE_MASK;
} else {
level <<= 1;
mask = BACKLIGHT_DUTY_CYCLE_MASK_PNV;
}
tmp = I915_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
tmp = I915_READ(BLC_PWM_CTL) & ~mask;
I915_WRITE(BLC_PWM_CTL, tmp | level);
}