drm/i915: Nuke drm_driver irq vfuncs
Stop using the irq vfuncs under drm_driver. That's not going to fly
in a mixed gen environment since the structure is shared between all
the devices.
v2: Allow intel_irq_uninstall() to be called twice due to
intel_modeset_cleanup() calling it as well. Toss in a
FIXME to remind us that this is not great.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190620103334.15651-1-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Ville Syrjälä
parent
08fa8fd0fa
commit
b318b82455
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@ -756,7 +756,7 @@ cleanup_gem:
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cleanup_modeset:
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intel_modeset_cleanup(dev);
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cleanup_irq:
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drm_irq_uninstall(dev);
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intel_irq_uninstall(dev_priv);
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intel_gmbus_teardown(dev_priv);
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cleanup_csr:
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intel_csr_ucode_fini(dev_priv);
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@ -2187,8 +2187,7 @@ static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
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static irqreturn_t valleyview_irq_handler(int irq, void *arg)
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{
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struct drm_device *dev = arg;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_i915_private *dev_priv = arg;
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irqreturn_t ret = IRQ_NONE;
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if (!intel_irqs_enabled(dev_priv))
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@ -2273,8 +2272,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
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static irqreturn_t cherryview_irq_handler(int irq, void *arg)
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{
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struct drm_device *dev = arg;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_i915_private *dev_priv = arg;
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irqreturn_t ret = IRQ_NONE;
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if (!intel_irqs_enabled(dev_priv))
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@ -2693,8 +2691,7 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
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*/
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static irqreturn_t ironlake_irq_handler(int irq, void *arg)
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{
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struct drm_device *dev = arg;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_i915_private *dev_priv = arg;
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u32 de_iir, gt_iir, de_ier, sde_ier = 0;
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irqreturn_t ret = IRQ_NONE;
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@ -3004,7 +3001,7 @@ static inline void gen8_master_intr_enable(void __iomem * const regs)
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static irqreturn_t gen8_irq_handler(int irq, void *arg)
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{
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struct drm_i915_private *dev_priv = to_i915(arg);
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struct drm_i915_private *dev_priv = arg;
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void __iomem * const regs = dev_priv->uncore.regs;
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u32 master_ctl;
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u32 gt_iir[4];
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@ -3203,7 +3200,7 @@ static inline void gen11_master_intr_enable(void __iomem * const regs)
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static irqreturn_t gen11_irq_handler(int irq, void *arg)
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{
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struct drm_i915_private * const i915 = to_i915(arg);
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struct drm_i915_private * const i915 = arg;
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void __iomem * const regs = i915->uncore.regs;
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u32 master_ctl;
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u32 gu_misc_iir;
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@ -3457,10 +3454,8 @@ static void ibx_irq_reset(struct drm_i915_private *dev_priv)
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*
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* This function needs to be called before interrupts are enabled.
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*/
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static void ibx_irq_pre_postinstall(struct drm_device *dev)
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static void ibx_irq_pre_postinstall(struct drm_i915_private *dev_priv)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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if (HAS_PCH_NOP(dev_priv))
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return;
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@ -3529,9 +3524,8 @@ static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
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/* drm_dma.h hooks
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*/
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static void ironlake_irq_reset(struct drm_device *dev)
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static void ironlake_irq_reset(struct drm_i915_private *dev_priv)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_uncore *uncore = &dev_priv->uncore;
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GEN3_IRQ_RESET(uncore, DE);
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@ -3548,10 +3542,8 @@ static void ironlake_irq_reset(struct drm_device *dev)
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ibx_irq_reset(dev_priv);
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}
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static void valleyview_irq_reset(struct drm_device *dev)
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static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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I915_WRITE(VLV_MASTER_IER, 0);
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POSTING_READ(VLV_MASTER_IER);
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@ -3573,9 +3565,8 @@ static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
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GEN8_IRQ_RESET_NDX(uncore, GT, 3);
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}
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static void gen8_irq_reset(struct drm_device *dev)
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static void gen8_irq_reset(struct drm_i915_private *dev_priv)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_uncore *uncore = &dev_priv->uncore;
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int pipe;
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@ -3618,9 +3609,8 @@ static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv)
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I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~0);
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}
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static void gen11_irq_reset(struct drm_device *dev)
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static void gen11_irq_reset(struct drm_i915_private *dev_priv)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_uncore *uncore = &dev_priv->uncore;
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int pipe;
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@ -3693,9 +3683,8 @@ void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
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synchronize_irq(dev_priv->drm.irq);
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}
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static void cherryview_irq_reset(struct drm_device *dev)
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static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_uncore *uncore = &dev_priv->uncore;
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I915_WRITE(GEN8_MASTER_IRQ, 0);
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@ -3960,9 +3949,8 @@ static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
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__bxt_hpd_detection_setup(dev_priv, enabled_irqs);
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}
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static void ibx_irq_postinstall(struct drm_device *dev)
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static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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u32 mask;
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if (HAS_PCH_NOP(dev_priv))
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@ -3985,9 +3973,8 @@ static void ibx_irq_postinstall(struct drm_device *dev)
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spt_hpd_detection_setup(dev_priv);
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}
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static void gen5_gt_irq_postinstall(struct drm_device *dev)
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static void gen5_gt_irq_postinstall(struct drm_i915_private *dev_priv)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_uncore *uncore = &dev_priv->uncore;
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u32 pm_irqs, gt_irqs;
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@ -4024,9 +4011,8 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
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}
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}
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static int ironlake_irq_postinstall(struct drm_device *dev)
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static void ironlake_irq_postinstall(struct drm_i915_private *dev_priv)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_uncore *uncore = &dev_priv->uncore;
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u32 display_mask, extra_mask;
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@ -4053,16 +4039,16 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
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dev_priv->irq_mask = ~display_mask;
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ibx_irq_pre_postinstall(dev);
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ibx_irq_pre_postinstall(dev_priv);
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GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,
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display_mask | extra_mask);
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gen5_gt_irq_postinstall(dev);
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gen5_gt_irq_postinstall(dev_priv);
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ilk_hpd_detection_setup(dev_priv);
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ibx_irq_postinstall(dev);
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ibx_irq_postinstall(dev_priv);
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if (IS_IRONLAKE_M(dev_priv)) {
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/* Enable PCU event interrupts
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@ -4074,8 +4060,6 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
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ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
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spin_unlock_irq(&dev_priv->irq_lock);
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}
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return 0;
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}
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void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
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@ -4107,11 +4091,9 @@ void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
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}
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static int valleyview_irq_postinstall(struct drm_device *dev)
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static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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gen5_gt_irq_postinstall(dev);
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gen5_gt_irq_postinstall(dev_priv);
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spin_lock_irq(&dev_priv->irq_lock);
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if (dev_priv->display_irqs_enabled)
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@ -4120,8 +4102,6 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
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I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
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POSTING_READ(VLV_MASTER_IER);
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return 0;
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}
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static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
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@ -4228,22 +4208,18 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
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}
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}
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static int gen8_irq_postinstall(struct drm_device *dev)
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static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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if (HAS_PCH_SPLIT(dev_priv))
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ibx_irq_pre_postinstall(dev);
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ibx_irq_pre_postinstall(dev_priv);
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gen8_gt_irq_postinstall(dev_priv);
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gen8_de_irq_postinstall(dev_priv);
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if (HAS_PCH_SPLIT(dev_priv))
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ibx_irq_postinstall(dev);
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ibx_irq_postinstall(dev_priv);
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gen8_master_intr_enable(dev_priv->uncore.regs);
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return 0;
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}
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static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
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@ -4277,9 +4253,8 @@ static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
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I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~0);
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}
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static void icp_irq_postinstall(struct drm_device *dev)
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static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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u32 mask = SDE_GMBUS_ICP;
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WARN_ON(I915_READ(SDEIER) != 0);
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@ -4292,14 +4267,13 @@ static void icp_irq_postinstall(struct drm_device *dev)
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icp_hpd_detection_setup(dev_priv);
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}
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static int gen11_irq_postinstall(struct drm_device *dev)
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static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_uncore *uncore = &dev_priv->uncore;
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u32 gu_misc_masked = GEN11_GU_MISC_GSE;
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if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
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icp_irq_postinstall(dev);
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icp_irq_postinstall(dev_priv);
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gen11_gt_irq_postinstall(dev_priv);
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gen8_de_irq_postinstall(dev_priv);
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@ -4310,14 +4284,10 @@ static int gen11_irq_postinstall(struct drm_device *dev)
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gen11_master_intr_enable(dev_priv->uncore.regs);
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POSTING_READ(GEN11_GFX_MSTR_IRQ);
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return 0;
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}
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static int cherryview_irq_postinstall(struct drm_device *dev)
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static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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gen8_gt_irq_postinstall(dev_priv);
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spin_lock_irq(&dev_priv->irq_lock);
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@ -4327,13 +4297,10 @@ static int cherryview_irq_postinstall(struct drm_device *dev)
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I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
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POSTING_READ(GEN8_MASTER_IRQ);
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return 0;
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}
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static void i8xx_irq_reset(struct drm_device *dev)
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static void i8xx_irq_reset(struct drm_i915_private *dev_priv)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_uncore *uncore = &dev_priv->uncore;
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i9xx_pipestat_irq_reset(dev_priv);
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@ -4341,9 +4308,8 @@ static void i8xx_irq_reset(struct drm_device *dev)
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GEN2_IRQ_RESET(uncore);
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}
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static int i8xx_irq_postinstall(struct drm_device *dev)
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static void i8xx_irq_postinstall(struct drm_i915_private *dev_priv)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_uncore *uncore = &dev_priv->uncore;
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u16 enable_mask;
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@ -4372,8 +4338,6 @@ static int i8xx_irq_postinstall(struct drm_device *dev)
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i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
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i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
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spin_unlock_irq(&dev_priv->irq_lock);
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return 0;
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}
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static void i8xx_error_irq_ack(struct drm_i915_private *i915,
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@ -4454,8 +4418,7 @@ static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv,
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static irqreturn_t i8xx_irq_handler(int irq, void *arg)
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{
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struct drm_device *dev = arg;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_i915_private *dev_priv = arg;
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irqreturn_t ret = IRQ_NONE;
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if (!intel_irqs_enabled(dev_priv))
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@ -4498,9 +4461,8 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
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return ret;
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}
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static void i915_irq_reset(struct drm_device *dev)
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static void i915_irq_reset(struct drm_i915_private *dev_priv)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_uncore *uncore = &dev_priv->uncore;
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if (I915_HAS_HOTPLUG(dev_priv)) {
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@ -4513,9 +4475,8 @@ static void i915_irq_reset(struct drm_device *dev)
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GEN3_IRQ_RESET(uncore, GEN2_);
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}
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static int i915_irq_postinstall(struct drm_device *dev)
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static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_uncore *uncore = &dev_priv->uncore;
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u32 enable_mask;
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@ -4553,14 +4514,11 @@ static int i915_irq_postinstall(struct drm_device *dev)
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spin_unlock_irq(&dev_priv->irq_lock);
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i915_enable_asle_pipestat(dev_priv);
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return 0;
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}
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static irqreturn_t i915_irq_handler(int irq, void *arg)
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{
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struct drm_device *dev = arg;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_i915_private *dev_priv = arg;
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irqreturn_t ret = IRQ_NONE;
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if (!intel_irqs_enabled(dev_priv))
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@ -4611,9 +4569,8 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
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return ret;
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}
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static void i965_irq_reset(struct drm_device *dev)
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static void i965_irq_reset(struct drm_i915_private *dev_priv)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_uncore *uncore = &dev_priv->uncore;
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i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
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@ -4624,9 +4581,8 @@ static void i965_irq_reset(struct drm_device *dev)
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GEN3_IRQ_RESET(uncore, GEN2_);
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}
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static int i965_irq_postinstall(struct drm_device *dev)
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static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_uncore *uncore = &dev_priv->uncore;
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u32 enable_mask;
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u32 error_mask;
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@ -4676,8 +4632,6 @@ static int i965_irq_postinstall(struct drm_device *dev)
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spin_unlock_irq(&dev_priv->irq_lock);
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||||
|
||||
i915_enable_asle_pipestat(dev_priv);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
|
||||
|
|
@ -4707,8 +4661,7 @@ static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
|
|||
|
||||
static irqreturn_t i965_irq_handler(int irq, void *arg)
|
||||
{
|
||||
struct drm_device *dev = arg;
|
||||
struct drm_i915_private *dev_priv = to_i915(dev);
|
||||
struct drm_i915_private *dev_priv = arg;
|
||||
irqreturn_t ret = IRQ_NONE;
|
||||
|
||||
if (!intel_irqs_enabled(dev_priv))
|
||||
|
|
@ -4839,65 +4792,18 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
|
|||
dev->driver->get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos;
|
||||
dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
|
||||
|
||||
if (IS_CHERRYVIEW(dev_priv)) {
|
||||
dev->driver->irq_handler = cherryview_irq_handler;
|
||||
dev->driver->irq_preinstall = cherryview_irq_reset;
|
||||
dev->driver->irq_postinstall = cherryview_irq_postinstall;
|
||||
dev->driver->irq_uninstall = cherryview_irq_reset;
|
||||
dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
|
||||
} else if (IS_VALLEYVIEW(dev_priv)) {
|
||||
dev->driver->irq_handler = valleyview_irq_handler;
|
||||
dev->driver->irq_preinstall = valleyview_irq_reset;
|
||||
dev->driver->irq_postinstall = valleyview_irq_postinstall;
|
||||
dev->driver->irq_uninstall = valleyview_irq_reset;
|
||||
dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
|
||||
} else if (INTEL_GEN(dev_priv) >= 11) {
|
||||
dev->driver->irq_handler = gen11_irq_handler;
|
||||
dev->driver->irq_preinstall = gen11_irq_reset;
|
||||
dev->driver->irq_postinstall = gen11_irq_postinstall;
|
||||
dev->driver->irq_uninstall = gen11_irq_reset;
|
||||
dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
|
||||
} else if (INTEL_GEN(dev_priv) >= 8) {
|
||||
dev->driver->irq_handler = gen8_irq_handler;
|
||||
dev->driver->irq_preinstall = gen8_irq_reset;
|
||||
dev->driver->irq_postinstall = gen8_irq_postinstall;
|
||||
dev->driver->irq_uninstall = gen8_irq_reset;
|
||||
if (IS_GEN9_LP(dev_priv))
|
||||
if (HAS_GMCH(dev_priv)) {
|
||||
if (I915_HAS_HOTPLUG(dev_priv))
|
||||
dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
|
||||
} else {
|
||||
if (INTEL_GEN(dev_priv) >= 11)
|
||||
dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
|
||||
else if (IS_GEN9_LP(dev_priv))
|
||||
dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
|
||||
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
|
||||
dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
|
||||
else
|
||||
dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
|
||||
} else if (HAS_PCH_SPLIT(dev_priv)) {
|
||||
dev->driver->irq_handler = ironlake_irq_handler;
|
||||
dev->driver->irq_preinstall = ironlake_irq_reset;
|
||||
dev->driver->irq_postinstall = ironlake_irq_postinstall;
|
||||
dev->driver->irq_uninstall = ironlake_irq_reset;
|
||||
dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
|
||||
} else {
|
||||
if (IS_GEN(dev_priv, 2)) {
|
||||
dev->driver->irq_preinstall = i8xx_irq_reset;
|
||||
dev->driver->irq_postinstall = i8xx_irq_postinstall;
|
||||
dev->driver->irq_handler = i8xx_irq_handler;
|
||||
dev->driver->irq_uninstall = i8xx_irq_reset;
|
||||
} else if (IS_I945GM(dev_priv)) {
|
||||
dev->driver->irq_preinstall = i915_irq_reset;
|
||||
dev->driver->irq_postinstall = i915_irq_postinstall;
|
||||
dev->driver->irq_uninstall = i915_irq_reset;
|
||||
dev->driver->irq_handler = i915_irq_handler;
|
||||
} else if (IS_GEN(dev_priv, 3)) {
|
||||
dev->driver->irq_preinstall = i915_irq_reset;
|
||||
dev->driver->irq_postinstall = i915_irq_postinstall;
|
||||
dev->driver->irq_uninstall = i915_irq_reset;
|
||||
dev->driver->irq_handler = i915_irq_handler;
|
||||
} else {
|
||||
dev->driver->irq_preinstall = i965_irq_reset;
|
||||
dev->driver->irq_postinstall = i965_irq_postinstall;
|
||||
dev->driver->irq_uninstall = i965_irq_reset;
|
||||
dev->driver->irq_handler = i965_irq_handler;
|
||||
}
|
||||
if (I915_HAS_HOTPLUG(dev_priv))
|
||||
dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -4918,6 +4824,75 @@ void intel_irq_fini(struct drm_i915_private *i915)
|
|||
kfree(i915->l3_parity.remap_info[i]);
|
||||
}
|
||||
|
||||
static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
if (HAS_GMCH(dev_priv)) {
|
||||
if (IS_CHERRYVIEW(dev_priv))
|
||||
return cherryview_irq_handler;
|
||||
else if (IS_VALLEYVIEW(dev_priv))
|
||||
return valleyview_irq_handler;
|
||||
else if (IS_GEN(dev_priv, 4))
|
||||
return i965_irq_handler;
|
||||
else if (IS_GEN(dev_priv, 3))
|
||||
return i915_irq_handler;
|
||||
else
|
||||
return i8xx_irq_handler;
|
||||
} else {
|
||||
if (INTEL_GEN(dev_priv) >= 11)
|
||||
return gen11_irq_handler;
|
||||
else if (INTEL_GEN(dev_priv) >= 8)
|
||||
return gen8_irq_handler;
|
||||
else
|
||||
return ironlake_irq_handler;
|
||||
}
|
||||
}
|
||||
|
||||
static void intel_irq_reset(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
if (HAS_GMCH(dev_priv)) {
|
||||
if (IS_CHERRYVIEW(dev_priv))
|
||||
cherryview_irq_reset(dev_priv);
|
||||
else if (IS_VALLEYVIEW(dev_priv))
|
||||
valleyview_irq_reset(dev_priv);
|
||||
else if (IS_GEN(dev_priv, 4))
|
||||
i965_irq_reset(dev_priv);
|
||||
else if (IS_GEN(dev_priv, 3))
|
||||
i915_irq_reset(dev_priv);
|
||||
else
|
||||
i8xx_irq_reset(dev_priv);
|
||||
} else {
|
||||
if (INTEL_GEN(dev_priv) >= 11)
|
||||
gen11_irq_reset(dev_priv);
|
||||
else if (INTEL_GEN(dev_priv) >= 8)
|
||||
gen8_irq_reset(dev_priv);
|
||||
else
|
||||
ironlake_irq_reset(dev_priv);
|
||||
}
|
||||
}
|
||||
|
||||
static void intel_irq_postinstall(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
if (HAS_GMCH(dev_priv)) {
|
||||
if (IS_CHERRYVIEW(dev_priv))
|
||||
cherryview_irq_postinstall(dev_priv);
|
||||
else if (IS_VALLEYVIEW(dev_priv))
|
||||
valleyview_irq_postinstall(dev_priv);
|
||||
else if (IS_GEN(dev_priv, 4))
|
||||
i965_irq_postinstall(dev_priv);
|
||||
else if (IS_GEN(dev_priv, 3))
|
||||
i915_irq_postinstall(dev_priv);
|
||||
else
|
||||
i8xx_irq_postinstall(dev_priv);
|
||||
} else {
|
||||
if (INTEL_GEN(dev_priv) >= 11)
|
||||
gen11_irq_postinstall(dev_priv);
|
||||
else if (INTEL_GEN(dev_priv) >= 8)
|
||||
gen8_irq_postinstall(dev_priv);
|
||||
else
|
||||
ironlake_irq_postinstall(dev_priv);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* intel_irq_install - enables the hardware interrupt
|
||||
* @dev_priv: i915 device instance
|
||||
|
|
@ -4931,6 +4906,9 @@ void intel_irq_fini(struct drm_i915_private *i915)
|
|||
*/
|
||||
int intel_irq_install(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
int irq = dev_priv->drm.pdev->irq;
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* We enable some interrupt sources in our postinstall hooks, so mark
|
||||
* interrupts as enabled _before_ actually enabling them to avoid
|
||||
|
|
@ -4938,7 +4916,20 @@ int intel_irq_install(struct drm_i915_private *dev_priv)
|
|||
*/
|
||||
dev_priv->runtime_pm.irqs_enabled = true;
|
||||
|
||||
return drm_irq_install(&dev_priv->drm, dev_priv->drm.pdev->irq);
|
||||
dev_priv->drm.irq_enabled = true;
|
||||
|
||||
intel_irq_reset(dev_priv);
|
||||
|
||||
ret = request_irq(irq, intel_irq_handler(dev_priv),
|
||||
IRQF_SHARED, DRIVER_NAME, dev_priv);
|
||||
if (ret < 0) {
|
||||
dev_priv->drm.irq_enabled = false;
|
||||
return ret;
|
||||
}
|
||||
|
||||
intel_irq_postinstall(dev_priv);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -4950,7 +4941,23 @@ int intel_irq_install(struct drm_i915_private *dev_priv)
|
|||
*/
|
||||
void intel_irq_uninstall(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
drm_irq_uninstall(&dev_priv->drm);
|
||||
int irq = dev_priv->drm.pdev->irq;
|
||||
|
||||
/*
|
||||
* FIXME we can get called twice during driver load
|
||||
* error handling due to intel_modeset_cleanup()
|
||||
* calling us out of sequence. Would be nice if
|
||||
* it didn't do that...
|
||||
*/
|
||||
if (!dev_priv->drm.irq_enabled)
|
||||
return;
|
||||
|
||||
dev_priv->drm.irq_enabled = false;
|
||||
|
||||
intel_irq_reset(dev_priv);
|
||||
|
||||
free_irq(irq, dev_priv);
|
||||
|
||||
intel_hpd_cancel_work(dev_priv);
|
||||
dev_priv->runtime_pm.irqs_enabled = false;
|
||||
}
|
||||
|
|
@ -4964,7 +4971,7 @@ void intel_irq_uninstall(struct drm_i915_private *dev_priv)
|
|||
*/
|
||||
void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
dev_priv->drm.driver->irq_uninstall(&dev_priv->drm);
|
||||
intel_irq_reset(dev_priv);
|
||||
dev_priv->runtime_pm.irqs_enabled = false;
|
||||
synchronize_irq(dev_priv->drm.irq);
|
||||
}
|
||||
|
|
@ -4979,6 +4986,6 @@ void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
|
|||
void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
dev_priv->runtime_pm.irqs_enabled = true;
|
||||
dev_priv->drm.driver->irq_preinstall(&dev_priv->drm);
|
||||
dev_priv->drm.driver->irq_postinstall(&dev_priv->drm);
|
||||
intel_irq_reset(dev_priv);
|
||||
intel_irq_postinstall(dev_priv);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue