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ice: introduce ice_ptp_init_phc function 

When we enable support for E822 devices, there are some additional
steps required to initialize the PTP hardware clock. To make this easier
to implement as device-specific behavior, refactor the register setups
in ice_ptp_init_owner to a new ice_ptp_init_phc function defined in
ice_ptp_hw.c

This function will have a common section, and an e810 specific
sub-implementation.

This will enable easily extending the functionality to cover the E822
specific setup required to initialize the hardware clock generation
unit. It also makes it clear which steps are E810 specific vs which ones
are necessary for all ice devices.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de>
Tested-by: Gurucharan G <gurucharanx.g@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
This commit is contained in:
Jacob Keller 2021-10-13 08:52:29 -07:00 committed by Tony Nguyen
parent 39b2810642
commit b2ee72565c
3 changed files with 55 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

53
drivers/net/ethernet/intel/ice/ice_ptp.c
View File

@ -1797,26 +1797,17 @@ void ice_ptp_reset(struct ice_pf *pf)
struct timespec64 ts;
u64 time_diff;
int err = 1;
u8 src_idx;
if (test_bit(ICE_PFR_REQ, pf->state))
goto pfr;
src_idx = hw->func_caps.ts_func_info.tmr_index_owned;
if (!hw->func_caps.ts_func_info.src_tmr_owned)
goto pfr;
wr32(hw, GLTSYN_SYNC_DLAY, 0);
/* Enable source clocks */
wr32(hw, GLTSYN_ENA(src_idx), GLTSYN_ENA_TSYN_ENA_M);
/* Enable PHY time sync */
err = ice_ptp_init_phy_e810(hw);
err = ice_ptp_init_phc(hw);
if (err)
goto err;
/* Clear event status indications for auxiliary pins */
(void)rd32(hw, GLTSYN_STAT(src_idx));
/* Acquire the global hardware lock */
if (!ice_ptp_lock(hw)) {
err = -EBUSY;
@ -1914,24 +1905,14 @@ static int ice_ptp_init_owner(struct ice_pf *pf)
{
struct ice_hw *hw = &pf->hw;
struct timespec64 ts;
u8 src_idx;
int err;
wr32(hw, GLTSYN_SYNC_DLAY, 0);
/* Clear some HW residue and enable source clock */
src_idx = hw->func_caps.ts_func_info.tmr_index_owned;
/* Enable source clocks */
wr32(hw, GLTSYN_ENA(src_idx), GLTSYN_ENA_TSYN_ENA_M);
/* Enable PHY time sync */
err = ice_ptp_init_phy_e810(hw);
if (err)
goto err_exit;
/* Clear event status indications for auxiliary pins */
(void)rd32(hw, GLTSYN_STAT(src_idx));
err = ice_ptp_init_phc(hw);
if (err) {
dev_err(ice_pf_to_dev(pf), "Failed to initialize PHC, err %d\n",
err);
return err;
}
/* Acquire the global hardware lock */
if (!ice_ptp_lock(hw)) {
@ -2003,12 +1984,16 @@ static int ice_ptp_init_work(struct ice_pf *pf, struct ice_ptp *ptp)
}
/**
* ice_ptp_init - Initialize the PTP support after device probe or reset
* ice_ptp_init - Initialize PTP hardware clock support
* @pf: Board private structure
*
* This function sets device up for PTP support. The first time it is run, it
* will create a clock device. It does not create a clock device if one
* already exists. It also reconfigures the device after a reset.
* Set up the device for interacting with the PTP hardware clock for all
* functions, both the function that owns the clock hardware, and the
* functions connected to the clock hardware.
*
* The clock owner will allocate and register a ptp_clock with the
* PTP_1588_CLOCK infrastructure. All functions allocate a kthread and work
* items used for asynchronous work such as Tx timestamps and periodic work.
*/
void ice_ptp_init(struct ice_pf *pf)
{
@ -2020,7 +2005,9 @@ void ice_ptp_init(struct ice_pf *pf)
if (!ice_is_e810(hw))
return;
/* Check if this PF owns the source timer */
/* If this function owns the clock hardware, it must allocate and
* configure the PTP clock device to represent it.
*/
if (hw->func_caps.ts_func_info.src_tmr_owned) {
err = ice_ptp_init_owner(pf);
if (err)

34
drivers/net/ethernet/intel/ice/ice_ptp_hw.c
View File

@ -213,6 +213,21 @@ int ice_ptp_init_phy_e810(struct ice_hw *hw)
return err;
}
/**
* ice_ptp_init_phc_e810 - Perform E810 specific PHC initialization
* @hw: pointer to HW struct
*
* Perform E810-specific PTP hardware clock initialization steps.
*/
static int ice_ptp_init_phc_e810(struct ice_hw *hw)
{
/* Ensure synchronization delay is zero */
wr32(hw, GLTSYN_SYNC_DLAY, 0);
/* Initialize the PHY */
return ice_ptp_init_phy_e810(hw);
}
/**
* ice_ptp_prep_phy_time_e810 - Prepare PHY port with initial time
* @hw: Board private structure
@ -800,3 +815,22 @@ bool ice_is_pca9575_present(struct ice_hw *hw)
return !status && handle;
}
/**
* ice_ptp_init_phc - Initialize PTP hardware clock
* @hw: pointer to the HW struct
*
* Perform the steps required to initialize the PTP hardware clock.
*/
int ice_ptp_init_phc(struct ice_hw *hw)
{
u8 src_idx = hw->func_caps.ts_func_info.tmr_index_owned;
/* Enable source clocks */
wr32(hw, GLTSYN_ENA(src_idx), GLTSYN_ENA_TSYN_ENA_M);
/* Clear event err indications for auxiliary pins */
(void)rd32(hw, GLTSYN_STAT(src_idx));
return ice_ptp_init_phc_e810(hw);
}

1
drivers/net/ethernet/intel/ice/ice_ptp_hw.h
View File

@ -27,6 +27,7 @@ int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval);
int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj);
int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp);
int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx);
int ice_ptp_init_phc(struct ice_hw *hw);
/* E810 family functions */
int ice_ptp_init_phy_e810(struct ice_hw *hw);