Merge branch 'x86/urgent' into x86/asm, to fix semantic conflict
'cpu_has_pse' has changed to boot_cpu_has(X86_FEATURE_PSE), fix this
up in the merge commit when merging the x86/urgent tree that includes
the following commit:
103f6112f2
("x86/mm/xen: Suppress hugetlbfs in PV guests")
Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
commit
b2eafe890d
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@ -19,7 +19,7 @@ ffffff0000000000 - ffffff7fffffffff (=39 bits) %esp fixup stacks
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ffffffef00000000 - ffffffff00000000 (=64 GB) EFI region mapping space
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ffffffef00000000 - ffffffff00000000 (=64 GB) EFI region mapping space
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... unused hole ...
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... unused hole ...
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ffffffff80000000 - ffffffffa0000000 (=512 MB) kernel text mapping, from phys 0
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ffffffff80000000 - ffffffffa0000000 (=512 MB) kernel text mapping, from phys 0
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ffffffffa0000000 - ffffffffff5fffff (=1525 MB) module mapping space
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ffffffffa0000000 - ffffffffff5fffff (=1526 MB) module mapping space
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ffffffffff600000 - ffffffffffdfffff (=8 MB) vsyscalls
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ffffffffff600000 - ffffffffffdfffff (=8 MB) vsyscalls
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ffffffffffe00000 - ffffffffffffffff (=2 MB) unused hole
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ffffffffffe00000 - ffffffffffffffff (=2 MB) unused hole
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@ -31,8 +31,8 @@ vmalloc space is lazily synchronized into the different PML4 pages of
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the processes using the page fault handler, with init_level4_pgt as
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the processes using the page fault handler, with init_level4_pgt as
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reference.
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reference.
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Current X86-64 implementations only support 40 bits of address space,
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Current X86-64 implementations support up to 46 bits of address space (64 TB),
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but we support up to 46 bits. This expands into MBZ space in the page tables.
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which is our current limit. This expands into MBZ space in the page tables.
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We map EFI runtime services in the 'efi_pgd' PGD in a 64Gb large virtual
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We map EFI runtime services in the 'efi_pgd' PGD in a 64Gb large virtual
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memory window (this size is arbitrary, it can be raised later if needed).
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memory window (this size is arbitrary, it can be raised later if needed).
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@ -4,6 +4,7 @@
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#include <asm/page.h>
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#include <asm/page.h>
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#include <asm-generic/hugetlb.h>
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#include <asm-generic/hugetlb.h>
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#define hugepages_supported() boot_cpu_has(X86_FEATURE_PSE)
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static inline int is_hugepage_only_range(struct mm_struct *mm,
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static inline int is_hugepage_only_range(struct mm_struct *mm,
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unsigned long addr,
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unsigned long addr,
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@ -152,6 +152,11 @@ static struct clocksource hyperv_cs = {
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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};
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static unsigned char hv_get_nmi_reason(void)
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{
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return 0;
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}
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static void __init ms_hyperv_init_platform(void)
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static void __init ms_hyperv_init_platform(void)
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{
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{
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/*
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/*
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@ -191,6 +196,13 @@ static void __init ms_hyperv_init_platform(void)
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machine_ops.crash_shutdown = hv_machine_crash_shutdown;
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machine_ops.crash_shutdown = hv_machine_crash_shutdown;
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#endif
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#endif
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mark_tsc_unstable("running on Hyper-V");
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mark_tsc_unstable("running on Hyper-V");
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/*
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* Generation 2 instances don't support reading the NMI status from
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* 0x61 port.
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*/
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if (efi_enabled(EFI_BOOT))
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x86_platform.get_nmi_reason = hv_get_nmi_reason;
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}
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}
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const __refconst struct hypervisor_x86 x86_hyper_ms_hyperv = {
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const __refconst struct hypervisor_x86 x86_hyper_ms_hyperv = {
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@ -362,6 +362,7 @@ struct sbridge_pvt {
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/* Memory type detection */
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/* Memory type detection */
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bool is_mirrored, is_lockstep, is_close_pg;
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bool is_mirrored, is_lockstep, is_close_pg;
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bool is_chan_hash;
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/* Fifo double buffers */
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/* Fifo double buffers */
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struct mce mce_entry[MCE_LOG_LEN];
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struct mce mce_entry[MCE_LOG_LEN];
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@ -1060,6 +1061,20 @@ static inline u8 sad_pkg_ha(u8 pkg)
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return (pkg >> 2) & 0x1;
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return (pkg >> 2) & 0x1;
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}
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}
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static int haswell_chan_hash(int idx, u64 addr)
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{
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int i;
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/*
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* XOR even bits from 12:26 to bit0 of idx,
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* odd bits from 13:27 to bit1
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*/
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for (i = 12; i < 28; i += 2)
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idx ^= (addr >> i) & 3;
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return idx;
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}
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/****************************************************************************
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/****************************************************************************
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Memory check routines
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Memory check routines
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****************************************************************************/
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****************************************************************************/
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@ -1616,6 +1631,10 @@ static int get_dimm_config(struct mem_ctl_info *mci)
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KNL_MAX_CHANNELS : NUM_CHANNELS;
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KNL_MAX_CHANNELS : NUM_CHANNELS;
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u64 knl_mc_sizes[KNL_MAX_CHANNELS];
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u64 knl_mc_sizes[KNL_MAX_CHANNELS];
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if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
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pci_read_config_dword(pvt->pci_ha0, HASWELL_HASYSDEFEATURE2, ®);
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pvt->is_chan_hash = GET_BITFIELD(reg, 21, 21);
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}
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if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL ||
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if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL ||
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pvt->info.type == KNIGHTS_LANDING)
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pvt->info.type == KNIGHTS_LANDING)
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pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, ®);
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pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, ®);
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@ -2118,12 +2137,15 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
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}
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}
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ch_way = TAD_CH(reg) + 1;
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ch_way = TAD_CH(reg) + 1;
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sck_way = 1 << TAD_SOCK(reg);
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sck_way = TAD_SOCK(reg);
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if (ch_way == 3)
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if (ch_way == 3)
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idx = addr >> 6;
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idx = addr >> 6;
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else
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else {
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idx = (addr >> (6 + sck_way + shiftup)) & 0x3;
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idx = (addr >> (6 + sck_way + shiftup)) & 0x3;
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if (pvt->is_chan_hash)
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idx = haswell_chan_hash(idx, addr);
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}
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idx = idx % ch_way;
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idx = idx % ch_way;
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/*
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/*
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@ -2157,7 +2179,7 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
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switch(ch_way) {
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switch(ch_way) {
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case 2:
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case 2:
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case 4:
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case 4:
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sck_xch = 1 << sck_way * (ch_way >> 1);
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sck_xch = (1 << sck_way) * (ch_way >> 1);
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break;
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break;
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default:
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default:
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sprintf(msg, "Invalid mirror set. Can't decode addr");
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sprintf(msg, "Invalid mirror set. Can't decode addr");
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@ -2193,7 +2215,7 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
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ch_addr = addr - offset;
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ch_addr = addr - offset;
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ch_addr >>= (6 + shiftup);
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ch_addr >>= (6 + shiftup);
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ch_addr /= ch_way * sck_way;
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ch_addr /= sck_xch;
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ch_addr <<= (6 + shiftup);
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ch_addr <<= (6 + shiftup);
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ch_addr |= addr & ((1 << (6 + shiftup)) - 1);
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ch_addr |= addr & ((1 << (6 + shiftup)) - 1);
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