irqchip/loongson-liointc: irqchip add 2.0 version
Add IO interrupt controller support for Loongson-2K1000, different from the Loongson-3A series is that Loongson-2K1000 has 64 interrupt sources, 0-31 correspond to the device tree liointc0 device node, and the other correspond to liointc1 node. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Qing Zhang <zhangqing@loongson.cn> Tested-by: Ming Wang <wangming01@loongson.cn> Acked-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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44151ea089
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b2c4c3969f
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@ -20,6 +20,7 @@
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#define LIOINTC_CHIP_IRQ 32
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#define LIOINTC_NUM_PARENT 4
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#define LIOINTC_NUM_CORES 4
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#define LIOINTC_INTC_CHIP_START 0x20
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@ -42,6 +43,7 @@ struct liointc_handler_data {
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struct liointc_priv {
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struct irq_chip_generic *gc;
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struct liointc_handler_data handler[LIOINTC_NUM_PARENT];
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void __iomem *core_isr[LIOINTC_NUM_CORES];
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u8 map_cache[LIOINTC_CHIP_IRQ];
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bool has_lpc_irq_errata;
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};
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@ -51,11 +53,12 @@ static void liointc_chained_handle_irq(struct irq_desc *desc)
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struct liointc_handler_data *handler = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct irq_chip_generic *gc = handler->priv->gc;
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int core = get_ebase_cpunum() % LIOINTC_NUM_CORES;
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u32 pending;
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chained_irq_enter(chip, desc);
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pending = readl(gc->reg_base + LIOINTC_REG_INTC_STATUS);
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pending = readl(handler->priv->core_isr[core]);
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if (!pending) {
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/* Always blame LPC IRQ if we have that bug */
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@ -141,6 +144,18 @@ static void liointc_resume(struct irq_chip_generic *gc)
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}
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static const char * const parent_names[] = {"int0", "int1", "int2", "int3"};
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static const char * const core_reg_names[] = {"isr0", "isr1", "isr2", "isr3"};
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static void __iomem *liointc_get_reg_byname(struct device_node *node,
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const char *name)
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{
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int index = of_property_match_string(node, "reg-names", name);
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if (index < 0)
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return NULL;
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return of_iomap(node, index);
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}
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static int __init liointc_of_init(struct device_node *node,
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struct device_node *parent)
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@ -159,10 +174,28 @@ static int __init liointc_of_init(struct device_node *node,
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if (!priv)
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return -ENOMEM;
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base = of_iomap(node, 0);
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if (!base) {
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err = -ENODEV;
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goto out_free_priv;
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if (of_device_is_compatible(node, "loongson,liointc-2.0")) {
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base = liointc_get_reg_byname(node, "main");
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if (!base) {
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err = -ENODEV;
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goto out_free_priv;
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}
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for (i = 0; i < LIOINTC_NUM_CORES; i++)
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priv->core_isr[i] = liointc_get_reg_byname(node, core_reg_names[i]);
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if (!priv->core_isr[0]) {
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err = -ENODEV;
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goto out_iounmap_base;
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}
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} else {
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base = of_iomap(node, 0);
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if (!base) {
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err = -ENODEV;
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goto out_free_priv;
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}
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for (i = 0; i < LIOINTC_NUM_CORES; i++)
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priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS;
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}
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for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
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@ -172,7 +205,7 @@ static int __init liointc_of_init(struct device_node *node,
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}
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if (!have_parent) {
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err = -ENODEV;
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goto out_iounmap;
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goto out_iounmap_isr;
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}
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sz = of_property_read_variable_u32_array(node,
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@ -183,7 +216,7 @@ static int __init liointc_of_init(struct device_node *node,
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if (sz < 4) {
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pr_err("loongson-liointc: No parent_int_map\n");
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err = -ENODEV;
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goto out_iounmap;
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goto out_iounmap_isr;
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}
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for (i = 0; i < LIOINTC_NUM_PARENT; i++)
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@ -195,7 +228,7 @@ static int __init liointc_of_init(struct device_node *node,
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if (!domain) {
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pr_err("loongson-liointc: cannot add IRQ domain\n");
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err = -EINVAL;
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goto out_iounmap;
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goto out_iounmap_isr;
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}
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err = irq_alloc_domain_generic_chips(domain, 32, 1,
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@ -260,7 +293,13 @@ static int __init liointc_of_init(struct device_node *node,
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out_free_domain:
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irq_domain_remove(domain);
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out_iounmap:
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out_iounmap_isr:
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for (i = 0; i < LIOINTC_NUM_CORES; i++) {
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if (!priv->core_isr[i])
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continue;
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iounmap(priv->core_isr[i]);
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}
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out_iounmap_base:
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iounmap(base);
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out_free_priv:
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kfree(priv);
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@ -270,3 +309,4 @@ out_free_priv:
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IRQCHIP_DECLARE(loongson_liointc_1_0, "loongson,liointc-1.0", liointc_of_init);
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IRQCHIP_DECLARE(loongson_liointc_1_0a, "loongson,liointc-1.0a", liointc_of_init);
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IRQCHIP_DECLARE(loongson_liointc_2_0, "loongson,liointc-2.0", liointc_of_init);
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