Merge branch 'imx/fixes-for-3.6' of git://git.linaro.org/people/shawnguo/linux-2.6 into fixes
* 'imx/fixes-for-3.6' of git://git.linaro.org/people/shawnguo/linux-2.6: ARM: dts: imx: fix gpio interrupts property ARM: dts: imx53-ard: add regulators for lan9220 ARM: imx: enable emi_slow_gate clock for imx5 ARM: imx6q-sabrelite: Setup CLKO IOMUX Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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commit
b29ee91c62
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@ -53,7 +53,7 @@
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spi-max-frequency = <6000000>;
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spi-max-frequency = <6000000>;
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reg = <0>;
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reg = <0>;
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interrupt-parent = <&gpio1>;
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interrupt-parent = <&gpio1>;
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interrupts = <8>;
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interrupts = <8 0x4>;
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regulators {
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regulators {
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sw1_reg: sw1 {
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sw1_reg: sw1 {
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@ -64,12 +64,32 @@
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reg = <0xf4000000 0x2000000>;
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reg = <0xf4000000 0x2000000>;
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phy-mode = "mii";
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phy-mode = "mii";
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interrupt-parent = <&gpio2>;
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interrupt-parent = <&gpio2>;
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interrupts = <31>;
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interrupts = <31 0x8>;
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reg-io-width = <4>;
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reg-io-width = <4>;
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/*
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* VDD33A and VDDVARIO of LAN9220 are supplied by
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* SW4_3V3 of LTC3589. Before the regulator driver
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* for this PMIC is available, we use a fixed dummy
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* 3V3 regulator to get LAN9220 driver probing work.
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*/
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vdd33a-supply = <®_3p3v>;
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vddvario-supply = <®_3p3v>;
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smsc,irq-push-pull;
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smsc,irq-push-pull;
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};
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};
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};
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};
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regulators {
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compatible = "simple-bus";
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reg_3p3v: 3p3v {
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compatible = "regulator-fixed";
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regulator-name = "3P3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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};
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gpio-keys {
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gpio-keys {
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compatible = "gpio-keys";
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compatible = "gpio-keys";
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@ -53,6 +53,7 @@
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fsl,pins = <
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fsl,pins = <
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144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
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144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
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121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
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121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
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953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */
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>;
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>;
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};
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};
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};
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};
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@ -303,6 +303,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
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clk_prepare_enable(clk[aips_tz2]); /* fec */
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clk_prepare_enable(clk[aips_tz2]); /* fec */
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clk_prepare_enable(clk[spba]);
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clk_prepare_enable(clk[spba]);
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clk_prepare_enable(clk[emi_fast_gate]); /* fec */
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clk_prepare_enable(clk[emi_fast_gate]); /* fec */
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clk_prepare_enable(clk[emi_slow_gate]); /* eim */
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clk_prepare_enable(clk[tmax1]);
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clk_prepare_enable(clk[tmax1]);
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clk_prepare_enable(clk[tmax2]); /* esdhc2, fec */
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clk_prepare_enable(clk[tmax2]); /* esdhc2, fec */
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clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */
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clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */
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