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ARM: dts: sti: update clkgen-pll entries in stih410-clock 

The clkgen-pll driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.

Signed-off-by: Alain Volmat <avolmat@me.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
This commit is contained in:
Alain Volmat 2021-03-31 22:42:20 +02:00 committed by Patrice Chotard
parent 9528bb46b6
commit b26ba00c3b
1 changed files with 3 additions and 13 deletions
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16
arch/arm/boot/dts/stih410-clock.dtsi
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@ -39,8 +39,6 @@
compatible = "st,stih407-clkgen-plla9"; compatible = "st,stih407-clkgen-plla9";
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
clock-output-names = "clockgen-a9-pll-odf";
}; };
}; };
@ -74,12 +72,9 @@
clk_s_a0_pll: clk-s-a0-pll { clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,clkgen-pll0"; compatible = "st,clkgen-pll0-a0";
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
clock-output-names = "clk-s-a0-pll-ofd-0";
clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
}; };
clk_s_a0_flexgen: clk-s-a0-flexgen { clk_s_a0_flexgen: clk-s-a0-flexgen {
@ -112,21 +107,16 @@
clk_s_c0_pll0: clk-s-c0-pll0 { clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,clkgen-pll0"; compatible = "st,clkgen-pll0-c0";
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
clock-output-names = "clk-s-c0-pll0-odf-0";
clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
}; };
clk_s_c0_pll1: clk-s-c0-pll1 { clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,clkgen-pll1"; compatible = "st,clkgen-pll1-c0";
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
clock-output-names = "clk-s-c0-pll1-odf-0";
}; };
clk_s_c0_flexgen: clk-s-c0-flexgen { clk_s_c0_flexgen: clk-s-c0-flexgen {