sh: Add SH-2A platform headers.
Mostly SH-2 wrappers.. Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Yoshinori Sato
Paul Mundt
parent
de39840646
commit
b229632abd
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@ -23,9 +23,13 @@ static void __init check_bugs(void)
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cpu_data->loops_per_jiffy = loops_per_jiffy;
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switch (cpu_data->type) {
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case CPU_SH7604:
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case CPU_SH7604 ... CPU_SH7619:
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*p++ = '2';
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break;
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case CPU_SH7206:
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*p++ = '2';
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*p++ = 'a';
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break;
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case CPU_SH7705 ... CPU_SH7300:
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*p++ = '3';
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break;
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@ -12,6 +12,7 @@
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#define L1_CACHE_SHIFT 4
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#if defined(CONFIG_CPU_SUBTYPE_SH7604)
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#define CCR 0xfffffe92 /* Address of Cache Control Register */
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#define CCR_CACHE_CE 0x01 /* Cache enable */
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@ -27,5 +28,26 @@
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#define CCR_CACHE_ORA CCR_CACHE_TW
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#define CCR_CACHE_WT 0x00 /* SH-2 is _always_ write-through */
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#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
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#define CCR1 0xffffffec
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#define CCR CCR1
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#define CCR_CACHE_CE 0x01 /* Cache enable */
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#define CCR_CACHE_WT 0x06 /* CCR[bit1=1,bit2=1] */
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/* 0x00000000-0x7fffffff: Write-through */
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/* 0x80000000-0x9fffffff: Write-back */
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/* 0xc0000000-0xdfffffff: Write-through */
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#define CCR_CACHE_CB 0x00 /* CCR[bit1=0,bit2=0] */
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/* 0x00000000-0x7fffffff: Write-back */
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/* 0x80000000-0x9fffffff: Write-through */
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/* 0xc0000000-0xdfffffff: Write-back */
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#define CCR_CACHE_CF 0x08 /* Cache invalidate */
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#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
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#define CACHE_OC_DATA_ARRAY 0xf1000000
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#define CCR_CACHE_ENABLE CCR_CACHE_CE
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#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
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#endif
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#endif /* __ASM_CPU_SH2_CACHE_H */
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@ -0,0 +1,18 @@
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/*
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* include/asm-sh/cpu-sh2/freq.h
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*
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* Copyright (C) 2006 Yoshinori Sato
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __ASM_CPU_SH2_FREQ_H
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#define __ASM_CPU_SH2_FREQ_H
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#if defined(CONFIG_CPU_SUBTYPE_SH7619)
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#define FREQCR 0xf815ff80
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#endif
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#endif /* __ASM_CPU_SH2_FREQ_H */
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@ -0,0 +1,84 @@
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#ifndef __ASM_SH_CPU_SH2_IRQ_H
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#define __ASM_SH_CPU_SH2_IRQ_H
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/*
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*
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* linux/include/asm-sh/cpu-sh2/irq.h
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*
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* Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
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* Copyright (C) 2000 Kazumoto Kojima
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* Copyright (C) 2003 Paul Mundt
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*
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*/
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#include <linux/config.h>
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#if defined(CONFIG_CPU_SUBTYPE_SH7044)
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#define INTC_IPRA 0xffff8348UL
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#define INTC_IPRB 0xffff834aUL
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#define INTC_IPRC 0xffff834cUL
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#define INTC_IPRD 0xffff834eUL
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#define INTC_IPRE 0xffff8350UL
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#define INTC_IPRF 0xffff8352UL
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#define INTC_IPRG 0xffff8354UL
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#define INTC_IPRH 0xffff8356UL
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#define INTC_ICR 0xffff8358UL
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#define INTC_ISR 0xffff835aUL
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#elif defined(CONFIG_CPU_SUBTYPE_SH7604)
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#define INTC_IPRA 0xfffffee2UL
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#define INTC_IPRB 0xfffffe60UL
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#define INTC_VCRA 0xfffffe62UL
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#define INTC_VCRB 0xfffffe64UL
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#define INTC_VCRC 0xfffffe66UL
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#define INTC_VCRD 0xfffffe68UL
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#define INTC_VCRWDT 0xfffffee4UL
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#define INTC_VCRDIV 0xffffff0cUL
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#define INTC_VCRDMA0 0xffffffa0UL
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#define INTC_VCRDMA1 0xffffffa8UL
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#define INTC_ICR 0xfffffee0UL
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#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
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#define INTC_IPRA 0xf8140006UL
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#define INTC_IPRB 0xf8140008UL
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#define INTC_IPRC 0xf8080000UL
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#define INTC_IPRD 0xf8080002UL
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#define INTC_IPRE 0xf8080004UL
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#define INTC_IPRF 0xf8080006UL
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#define INTC_IPRG 0xf8080008UL
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#define INTC_ICR0 0xf8140000UL
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#define INTC_IRQCR 0xf8140002UL
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#define INTC_IRQSR 0xf8140004UL
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#define CMI0_IRQ 86
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#define CMI1_IRQ 87
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#define SCIF_ERI_IRQ 88
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#define SCIF_RXI_IRQ 89
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#define SCIF_BRI_IRQ 90
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#define SCIF_TXI_IRQ 91
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#define SCIF_IPR_ADDR INTC_IPRD
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#define SCIF_IPR_POS 3
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#define SCIF_PRIORITY 3
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#define SCIF1_ERI_IRQ 92
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#define SCIF1_RXI_IRQ 93
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#define SCIF1_BRI_IRQ 94
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#define SCIF1_TXI_IRQ 95
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#define SCIF1_IPR_ADDR INTC_IPRD
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#define SCIF1_IPR_POS 2
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#define SCIF1_PRIORITY 3
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#define SCIF2_BRI_IRQ 96
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#define SCIF2_RXI_IRQ 97
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#define SCIF2_ERI_IRQ 98
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#define SCIF2_TXI_IRQ 99
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#define SCIF2_IPR_ADDR INTC_IPRD
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#define SCIF2_IPR_POS 1
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#define SCIF2_PRIORITY 3
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#endif
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#endif /* __ASM_SH_CPU_SH2_IRQ_H */
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@ -0,0 +1,16 @@
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/*
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* include/asm-sh/cpu-sh2/mmu_context.h
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*
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* Copyright (C) 2003 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __ASM_CPU_SH2_MMU_CONTEXT_H
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#define __ASM_CPU_SH2_MMU_CONTEXT_H
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/* No MMU */
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#endif /* __ASM_CPU_SH2_MMU_CONTEXT_H */
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@ -0,0 +1 @@
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#include <asm/cpu-sh2/addrspace.h>
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@ -0,0 +1,39 @@
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/*
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* include/asm-sh/cpu-sh2a/cache.h
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*
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* Copyright (C) 2004 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __ASM_CPU_SH2A_CACHE_H
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#define __ASM_CPU_SH2A_CACHE_H
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#define L1_CACHE_SHIFT 4
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#define CCR1 0xfffc1000
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#define CCR2 0xfffc1004
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/* CCR1 behaves more like the traditional CCR */
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#define CCR CCR1
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/*
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* Most of the SH-2A CCR1 definitions resemble the SH-4 ones. All others not
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* listed here are reserved.
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*/
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#define CCR_CACHE_CB 0x0000 /* Hack */
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#define CCR_CACHE_OCE 0x0001
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#define CCR_CACHE_WT 0x0002
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#define CCR_CACHE_OCI 0x0008 /* OCF */
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#define CCR_CACHE_ICE 0x0100
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#define CCR_CACHE_ICI 0x0800 /* ICF */
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#define CACHE_IC_ADDRESS_ARRAY 0xf0000000
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#define CACHE_OC_ADDRESS_ARRAY 0xf0800000
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#define CCR_CACHE_ENABLE (CCR_CACHE_OCE | CCR_CACHE_ICE)
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#define CCR_CACHE_INVALIDATE (CCR_CACHE_OCI | CCR_CACHE_ICI)
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#endif /* __ASM_CPU_SH2A_CACHE_H */
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@ -0,0 +1 @@
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#include <asm/cpu-sh2/cacheflush.h>
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@ -0,0 +1 @@
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#include <asm/cpu-sh2/dma.h>
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@ -0,0 +1,18 @@
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/*
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* include/asm-sh/cpu-sh2a/freq.h
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*
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* Copyright (C) 2006 Yoshinori Sato
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __ASM_CPU_SH2A_FREQ_H
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#define __ASM_CPU_SH2A_FREQ_H
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#if defined(CONFIG_CPU_SUBTYPE_SH7206)
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#define FREQCR 0xfffe0010
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#endif
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#endif /* __ASM_CPU_SH2A_FREQ_H */
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@ -0,0 +1,75 @@
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#ifndef __ASM_SH_CPU_SH2A_IRQ_H
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#define __ASM_SH_CPU_SH2A_IRQ_H
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#define INTC_IPR01 0xfffe0818UL
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#define INTC_IPR02 0xfffe081aUL
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#define INTC_IPR05 0xfffe0820UL
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#define INTC_IPR06 0xfffe0c00UL
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#define INTC_IPR07 0xfffe0c02UL
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#define INTC_IPR08 0xfffe0c04UL
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#define INTC_IPR09 0xfffe0c06UL
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#define INTC_IPR10 0xfffe0c08UL
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#define INTC_IPR11 0xfffe0c0aUL
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#define INTC_IPR12 0xfffe0c0cUL
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#define INTC_IPR13 0xfffe0c0eUL
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#define INTC_IPR14 0xfffe0c10UL
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#define INTC_ICR0 0xfffe0800UL
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#define INTC_ICR1 0xfffe0802UL
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#define INTC_ICR2 0xfffe0804UL
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#define INTC_ISR 0xfffe0806UL
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#define IRQ0_IRQ 64
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#define IRQ1_IRQ 65
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#define IRQ2_IRQ 66
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#define IRQ3_IRQ 67
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#define IRQ4_IRQ 68
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#define IRQ5_IRQ 69
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#define IRQ6_IRQ 70
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#define IRQ7_IRQ 71
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#define PINT0_IRQ 80
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#define PINT1_IRQ 81
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#define PINT2_IRQ 82
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#define PINT3_IRQ 83
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#define PINT4_IRQ 84
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#define PINT5_IRQ 85
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#define PINT6_IRQ 86
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#define PINT7_IRQ 87
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#define CMI0_IRQ 140
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#define CMI1_IRQ 141
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#define SCIF_BRI_IRQ 240
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#define SCIF_ERI_IRQ 241
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#define SCIF_RXI_IRQ 242
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#define SCIF_TXI_IRQ 243
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#define SCIF_IPR_ADDR INTC_IPR14
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#define SCIF_IPR_POS 3
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#define SCIF_PRIORITY 3
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#define SCIF1_BRI_IRQ 244
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#define SCIF1_ERI_IRQ 245
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#define SCIF1_RXI_IRQ 246
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#define SCIF1_TXI_IRQ 247
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#define SCIF1_IPR_ADDR INTC_IPR14
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#define SCIF1_IPR_POS 2
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#define SCIF1_PRIORITY 3
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#define SCIF2_BRI_IRQ 248
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#define SCIF2_ERI_IRQ 249
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#define SCIF2_RXI_IRQ 250
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#define SCIF2_TXI_IRQ 251
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#define SCIF2_IPR_ADDR INTC_IPR14
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#define SCIF2_IPR_POS 1
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#define SCIF2_PRIORITY 3
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#define SCIF3_BRI_IRQ 252
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#define SCIF3_ERI_IRQ 253
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#define SCIF3_RXI_IRQ 254
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#define SCIF3_TXI_IRQ 255
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#define SCIF3_IPR_ADDR INTC_IPR14
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#define SCIF3_IPR_POS 0
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#define SCIF3_PRIORITY 3
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#endif /* __ASM_SH_CPU_SH2A_IRQ_H */
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@ -0,0 +1 @@
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#include <asm/cpu-sh2/mmu_context.h>
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@ -0,0 +1 @@
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#include <asm/cpu-sh2/timer.h>
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@ -0,0 +1 @@
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#include <asm/cpu-sh2/ubc.h>
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@ -0,0 +1 @@
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#include <asm/cpu-sh2/watchdog.h>
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@ -0,0 +1,32 @@
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! entry.S macro define
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.macro cli
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stc sr, r0
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or #0xf0, r0
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ldc r0, sr
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.endm
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.macro sti
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mov #0xf0, r11
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extu.b r11, r11
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not r11, r11
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stc sr, r10
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and r11, r10
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#ifdef CONFIG_HAS_SR_RB
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stc k_g_imask, r11
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or r11, r10
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#endif
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ldc r10, sr
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.endm
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.macro get_current_thread_info, ti, tmp
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#ifdef CONFIG_HAS_SR_RB
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stc r7_bank, \ti
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#else
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mov #((THREAD_SIZE - 1)>> 8) ^ 0xff, \tmp
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shll8 \tmp
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mov r15, \ti
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and \tmp, \ti
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#endif
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.endm
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@ -14,6 +14,10 @@
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#include <asm/machvec.h>
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#include <asm/ptrace.h> /* for pt_regs */
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#if defined(CONFIG_CPU_SH2)
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#include <asm/cpu/irq.h>
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#endif
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#ifndef CONFIG_CPU_SUBTYPE_SH7780
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#define INTC_DMAC0_MSK 0
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@ -28,6 +32,31 @@
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#define INTC_IPRD 0xffd00010UL
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7206)
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#ifdef CONFIG_SH_CMT
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#define TIMER_IRQ CMI0_IRQ
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#define TIMER_IPR_ADDR INTC_IPR08
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#define TIMER_IPR_POS 3
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#define TIMER_PRIORITY 2
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#define TIMER1_IRQ CMI1_IRQ
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#define TIMER1_IPR_ADDR INTC_IPR08
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#define TIMER1_IPR_POS 2
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#define TIMER1_PRIORITY 2
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#endif
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#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
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#define TIMER_IRQ CMI0_IRQ
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#define TIMER_IPR_ADDR INTC_IPRC
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#define TIMER_IPR_POS 1
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#define TIMER_PRIORITY 2
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#define TIMER1_IRQ CMI1_IRQ
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#define TIMER1_IPR_ADDR INTC_IPRC
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#define TIMER1_IPR_POS 0
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#define TIMER1_PRIORITY 4
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#else
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#define TIMER_IRQ 16
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#define TIMER_IPR_ADDR INTC_IPRA
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#define TIMER_IPR_POS 3
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@ -37,11 +66,14 @@
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#define TIMER1_IPR_ADDR INTC_IPRA
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#define TIMER1_IPR_POS 2
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#define TIMER1_PRIORITY 4
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#endif
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#if !defined(CONFIG_CPU_SH2)
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#define RTC_IRQ 22
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#define RTC_IPR_ADDR INTC_IPRA
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#define RTC_IPR_POS 0
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#define RTC_PRIORITY TIMER_PRIORITY
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#endif
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#if defined(CONFIG_CPU_SH3)
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#define DMTE0_IRQ 48
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@ -265,6 +297,10 @@
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# define ONCHIP_NR_IRQS 109
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#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
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# define ONCHIP_NR_IRQS 111
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#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
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# define ONCHIP_NR_IRQS 256
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#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
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# define ONCHIP_NR_IRQS 128
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#elif defined(CONFIG_SH_UNKNOWN) /* Most be last */
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# define ONCHIP_NR_IRQS 144
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#endif
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@ -322,6 +358,40 @@ extern void enable_irq(unsigned int);
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extern void make_maskreg_irq(unsigned int irq);
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extern unsigned short *irq_mask_register;
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#if defined(CONFIG_CPU_SUBTYPE_SH7619)
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#define IRQ0_IRQ 16
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#define IRQ1_IRQ 17
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#define IRQ2_IRQ 18
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#define IRQ3_IRQ 19
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#define IRQ4_IRQ 32
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#define IRQ5_IRQ 33
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#define IRQ6_IRQ 34
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#define IRQ7_IRQ 35
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#elif !defined(CONFIG_CPU_SUBTYPE_SH7206)
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#define IRQ0_IRQ 32
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#define IRQ1_IRQ 33
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#define IRQ2_IRQ 34
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#define IRQ3_IRQ 35
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#define IRQ4_IRQ 36
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#define IRQ5_IRQ 37
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#endif
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#define IRQ0_PRIORITY 1
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#define IRQ1_PRIORITY 1
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#define IRQ2_PRIORITY 1
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#define IRQ3_PRIORITY 1
|
||||
#define IRQ4_PRIORITY 1
|
||||
#define IRQ5_PRIORITY 1
|
||||
|
||||
#ifndef IRQ0_IPR_POS
|
||||
#define IRQ0_IPR_POS 0
|
||||
#define IRQ1_IPR_POS 1
|
||||
#define IRQ2_IPR_POS 2
|
||||
#define IRQ3_IPR_POS 3
|
||||
#define IRQ4_IPR_POS 0
|
||||
#define IRQ5_IPR_POS 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* PINT IRQs
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -36,7 +36,10 @@
|
|||
*/
|
||||
enum cpu_type {
|
||||
/* SH-2 types */
|
||||
CPU_SH7604,
|
||||
CPU_SH7604, CPU_SH7619,
|
||||
|
||||
/* SH-2A types */
|
||||
CPU_SH7206,
|
||||
|
||||
/* SH-3 types */
|
||||
CPU_SH7705, CPU_SH7706, CPU_SH7707,
|
||||
|
|
|
|||
|
|
@ -349,12 +349,30 @@ do { \
|
|||
return (type) (res); \
|
||||
} while (0)
|
||||
|
||||
#if defined(__sh2__) || defined(__SH2E__) || defined(__SH2A__)
|
||||
#define SYSCALL_ARG0 "trapa #0x20"
|
||||
#define SYSCALL_ARG1 "trapa #0x21"
|
||||
#define SYSCALL_ARG2 "trapa #0x22"
|
||||
#define SYSCALL_ARG3 "trapa #0x23"
|
||||
#define SYSCALL_ARG4 "trapa #0x24"
|
||||
#define SYSCALL_ARG5 "trapa #0x25"
|
||||
#define SYSCALL_ARG6 "trapa #0x26"
|
||||
#else
|
||||
#define SYSCALL_ARG0 "trapa #0x10"
|
||||
#define SYSCALL_ARG1 "trapa #0x11"
|
||||
#define SYSCALL_ARG2 "trapa #0x12"
|
||||
#define SYSCALL_ARG3 "trapa #0x13"
|
||||
#define SYSCALL_ARG4 "trapa #0x14"
|
||||
#define SYSCALL_ARG5 "trapa #0x15"
|
||||
#define SYSCALL_ARG6 "trapa #0x16"
|
||||
#endif
|
||||
|
||||
/* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */
|
||||
#define _syscall0(type,name) \
|
||||
type name(void) \
|
||||
{ \
|
||||
register long __sc0 __asm__ ("r3") = __NR_##name; \
|
||||
__asm__ __volatile__ ("trapa #0x10" \
|
||||
__asm__ __volatile__ (SYSCALL_ARG0 \
|
||||
: "=z" (__sc0) \
|
||||
: "0" (__sc0) \
|
||||
: "memory" ); \
|
||||
|
|
@ -366,7 +384,7 @@ type name(type1 arg1) \
|
|||
{ \
|
||||
register long __sc0 __asm__ ("r3") = __NR_##name; \
|
||||
register long __sc4 __asm__ ("r4") = (long) arg1; \
|
||||
__asm__ __volatile__ ("trapa #0x11" \
|
||||
__asm__ __volatile__ (SYSCALL_ARG1 \
|
||||
: "=z" (__sc0) \
|
||||
: "0" (__sc0), "r" (__sc4) \
|
||||
: "memory"); \
|
||||
|
|
@ -379,7 +397,7 @@ type name(type1 arg1,type2 arg2) \
|
|||
register long __sc0 __asm__ ("r3") = __NR_##name; \
|
||||
register long __sc4 __asm__ ("r4") = (long) arg1; \
|
||||
register long __sc5 __asm__ ("r5") = (long) arg2; \
|
||||
__asm__ __volatile__ ("trapa #0x12" \
|
||||
__asm__ __volatile__ (SYSCALL_ARG2 \
|
||||
: "=z" (__sc0) \
|
||||
: "0" (__sc0), "r" (__sc4), "r" (__sc5) \
|
||||
: "memory"); \
|
||||
|
|
@ -393,7 +411,7 @@ register long __sc0 __asm__ ("r3") = __NR_##name; \
|
|||
register long __sc4 __asm__ ("r4") = (long) arg1; \
|
||||
register long __sc5 __asm__ ("r5") = (long) arg2; \
|
||||
register long __sc6 __asm__ ("r6") = (long) arg3; \
|
||||
__asm__ __volatile__ ("trapa #0x13" \
|
||||
__asm__ __volatile__ (SYSCALL_ARG3 \
|
||||
: "=z" (__sc0) \
|
||||
: "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6) \
|
||||
: "memory"); \
|
||||
|
|
@ -408,7 +426,7 @@ register long __sc4 __asm__ ("r4") = (long) arg1; \
|
|||
register long __sc5 __asm__ ("r5") = (long) arg2; \
|
||||
register long __sc6 __asm__ ("r6") = (long) arg3; \
|
||||
register long __sc7 __asm__ ("r7") = (long) arg4; \
|
||||
__asm__ __volatile__ ("trapa #0x14" \
|
||||
__asm__ __volatile__ (SYSCALL_ARG4 \
|
||||
: "=z" (__sc0) \
|
||||
: "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6), \
|
||||
"r" (__sc7) \
|
||||
|
|
@ -425,7 +443,7 @@ register long __sc5 __asm__ ("r5") = (long) arg2; \
|
|||
register long __sc6 __asm__ ("r6") = (long) arg3; \
|
||||
register long __sc7 __asm__ ("r7") = (long) arg4; \
|
||||
register long __sc0 __asm__ ("r0") = (long) arg5; \
|
||||
__asm__ __volatile__ ("trapa #0x15" \
|
||||
__asm__ __volatile__ (SYSCALL_ARG5 \
|
||||
: "=z" (__sc0) \
|
||||
: "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6), "r" (__sc7), \
|
||||
"r" (__sc3) \
|
||||
|
|
@ -443,7 +461,7 @@ register long __sc6 __asm__ ("r6") = (long) arg3; \
|
|||
register long __sc7 __asm__ ("r7") = (long) arg4; \
|
||||
register long __sc0 __asm__ ("r0") = (long) arg5; \
|
||||
register long __sc1 __asm__ ("r1") = (long) arg6; \
|
||||
__asm__ __volatile__ ("trapa #0x16" \
|
||||
__asm__ __volatile__ (SYSCALL_ARG6 \
|
||||
: "=z" (__sc0) \
|
||||
: "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6), "r" (__sc7), \
|
||||
"r" (__sc3), "r" (__sc1) \
|
||||
|
|
|
|||
Loading…
Reference in New Issue