drm/gma500: Make SGX MMU driver actually do something
Old MMU code never wrote PDs or PTEs to any registers. Now we do, and that's a good start. Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
This commit is contained in:
Patrik Jakobsson
parent
786a7828bc
commit
b219372dff
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@ -59,15 +59,14 @@ struct psb_mmu_driver {
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spinlock_t lock;
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atomic_t needs_tlbflush;
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uint8_t __iomem *register_map;
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atomic_t *msvdx_mmu_invaldc;
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struct psb_mmu_pd *default_pd;
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/*uint32_t bif_ctrl;*/
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uint32_t bif_ctrl;
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int has_clflush;
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int clflush_add;
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unsigned long clflush_mask;
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struct drm_psb_private *dev_priv;
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struct drm_device *dev;
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};
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struct psb_mmu_pd;
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@ -102,13 +101,13 @@ static inline uint32_t psb_mmu_pd_index(uint32_t offset)
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return offset >> PSB_PDE_SHIFT;
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}
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#if defined(CONFIG_X86)
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static inline void psb_clflush(void *addr)
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{
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__asm__ __volatile__("clflush (%0)\n" : : "r"(addr) : "memory");
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}
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static inline void psb_mmu_clflush(struct psb_mmu_driver *driver,
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void *addr)
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static inline void psb_mmu_clflush(struct psb_mmu_driver *driver, void *addr)
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{
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if (!driver->has_clflush)
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return;
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@ -117,62 +116,77 @@ static inline void psb_mmu_clflush(struct psb_mmu_driver *driver,
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psb_clflush(addr);
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mb();
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}
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#else
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static void psb_page_clflush(struct psb_mmu_driver *driver, struct page* page)
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static inline void psb_mmu_clflush(struct psb_mmu_driver *driver, void *addr)
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{;
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}
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#endif
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static void psb_mmu_flush_pd_locked(struct psb_mmu_driver *driver, int force)
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{
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uint32_t clflush_add = driver->clflush_add >> PAGE_SHIFT;
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uint32_t clflush_count = PAGE_SIZE / clflush_add;
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int i;
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uint8_t *clf;
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struct drm_device *dev = driver->dev;
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struct drm_psb_private *dev_priv = dev->dev_private;
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clf = kmap_atomic(page);
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mb();
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for (i = 0; i < clflush_count; ++i) {
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psb_clflush(clf);
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clf += clflush_add;
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if (atomic_read(&driver->needs_tlbflush) || force) {
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uint32_t val = PSB_RSGX32(PSB_CR_BIF_CTRL);
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PSB_WSGX32(val | _PSB_CB_CTRL_INVALDC, PSB_CR_BIF_CTRL);
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/* Make sure data cache is turned off before enabling it */
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wmb();
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PSB_WSGX32(val & ~_PSB_CB_CTRL_INVALDC, PSB_CR_BIF_CTRL);
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(void)PSB_RSGX32(PSB_CR_BIF_CTRL);
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if (driver->msvdx_mmu_invaldc)
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atomic_set(driver->msvdx_mmu_invaldc, 1);
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}
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mb();
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kunmap_atomic(clf);
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}
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static void psb_pages_clflush(struct psb_mmu_driver *driver,
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struct page *page[], unsigned long num_pages)
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{
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int i;
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if (!driver->has_clflush)
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return ;
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for (i = 0; i < num_pages; i++)
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psb_page_clflush(driver, *page++);
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}
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static void psb_mmu_flush_pd_locked(struct psb_mmu_driver *driver,
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int force)
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{
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atomic_set(&driver->needs_tlbflush, 0);
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}
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#if 0
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static void psb_mmu_flush_pd(struct psb_mmu_driver *driver, int force)
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{
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down_write(&driver->sem);
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psb_mmu_flush_pd_locked(driver, force);
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up_write(&driver->sem);
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}
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#endif
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void psb_mmu_flush(struct psb_mmu_driver *driver, int rc_prot)
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void psb_mmu_flush(struct psb_mmu_driver *driver)
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{
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if (rc_prot)
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down_write(&driver->sem);
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if (rc_prot)
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up_write(&driver->sem);
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struct drm_device *dev = driver->dev;
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struct drm_psb_private *dev_priv = dev->dev_private;
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uint32_t val;
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down_write(&driver->sem);
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val = PSB_RSGX32(PSB_CR_BIF_CTRL);
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if (atomic_read(&driver->needs_tlbflush))
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PSB_WSGX32(val | _PSB_CB_CTRL_INVALDC, PSB_CR_BIF_CTRL);
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else
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PSB_WSGX32(val | _PSB_CB_CTRL_FLUSH, PSB_CR_BIF_CTRL);
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/* Make sure data cache is turned off and MMU is flushed before
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restoring bank interface control register */
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wmb();
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PSB_WSGX32(val & ~(_PSB_CB_CTRL_FLUSH | _PSB_CB_CTRL_INVALDC),
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PSB_CR_BIF_CTRL);
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(void)PSB_RSGX32(PSB_CR_BIF_CTRL);
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atomic_set(&driver->needs_tlbflush, 0);
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if (driver->msvdx_mmu_invaldc)
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atomic_set(driver->msvdx_mmu_invaldc, 1);
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up_write(&driver->sem);
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}
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void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context)
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{
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/*ttm_tt_cache_flush(&pd->p, 1);*/
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psb_pages_clflush(pd->driver, &pd->p, 1);
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struct drm_device *dev = pd->driver->dev;
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struct drm_psb_private *dev_priv = dev->dev_private;
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uint32_t offset = (hw_context == 0) ? PSB_CR_BIF_DIR_LIST_BASE0 :
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PSB_CR_BIF_DIR_LIST_BASE1 + hw_context * 4;
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down_write(&pd->driver->sem);
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PSB_WSGX32(page_to_pfn(pd->p) << PAGE_SHIFT, offset);
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wmb();
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psb_mmu_flush_pd_locked(pd->driver, 1);
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pd->hw_context = hw_context;
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@ -183,7 +197,6 @@ void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context)
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static inline unsigned long psb_pd_addr_end(unsigned long addr,
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unsigned long end)
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{
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addr = (addr + PSB_PDE_MASK + 1) & ~PSB_PDE_MASK;
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return (addr < end) ? addr : end;
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}
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@ -223,12 +236,10 @@ struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
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goto out_err3;
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if (!trap_pagefaults) {
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pd->invalid_pde =
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psb_mmu_mask_pte(page_to_pfn(pd->dummy_pt),
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invalid_type);
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pd->invalid_pte =
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psb_mmu_mask_pte(page_to_pfn(pd->dummy_page),
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invalid_type);
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pd->invalid_pde = psb_mmu_mask_pte(page_to_pfn(pd->dummy_pt),
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invalid_type);
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pd->invalid_pte = psb_mmu_mask_pte(page_to_pfn(pd->dummy_page),
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invalid_type);
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} else {
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pd->invalid_pde = 0;
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pd->invalid_pte = 0;
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@ -279,12 +290,16 @@ static void psb_mmu_free_pt(struct psb_mmu_pt *pt)
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void psb_mmu_free_pagedir(struct psb_mmu_pd *pd)
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{
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struct psb_mmu_driver *driver = pd->driver;
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struct drm_device *dev = driver->dev;
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct psb_mmu_pt *pt;
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int i;
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down_write(&driver->sem);
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if (pd->hw_context != -1)
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if (pd->hw_context != -1) {
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PSB_WSGX32(0, PSB_CR_BIF_DIR_LIST_BASE0 + pd->hw_context * 4);
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psb_mmu_flush_pd_locked(driver, 1);
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}
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/* Should take the spinlock here, but we don't need to do that
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since we have the semaphore in write mode. */
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@ -331,7 +346,7 @@ static struct psb_mmu_pt *psb_mmu_alloc_pt(struct psb_mmu_pd *pd)
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for (i = 0; i < (PAGE_SIZE / sizeof(uint32_t)); ++i)
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*ptes++ = pd->invalid_pte;
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#if defined(CONFIG_X86)
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if (pd->driver->has_clflush && pd->hw_context != -1) {
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mb();
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for (i = 0; i < clflush_count; ++i) {
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@ -340,7 +355,7 @@ static struct psb_mmu_pt *psb_mmu_alloc_pt(struct psb_mmu_pd *pd)
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}
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mb();
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}
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#endif
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kunmap_atomic(v);
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spin_unlock(lock);
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@ -351,7 +366,7 @@ static struct psb_mmu_pt *psb_mmu_alloc_pt(struct psb_mmu_pd *pd)
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return pt;
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}
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static struct psb_mmu_pt *psb_mmu_pt_alloc_map_lock(struct psb_mmu_pd *pd,
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struct psb_mmu_pt *psb_mmu_pt_alloc_map_lock(struct psb_mmu_pd *pd,
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unsigned long addr)
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{
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uint32_t index = psb_mmu_pd_index(addr);
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@ -383,7 +398,7 @@ static struct psb_mmu_pt *psb_mmu_pt_alloc_map_lock(struct psb_mmu_pd *pd,
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kunmap_atomic((void *) v);
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if (pd->hw_context != -1) {
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psb_mmu_clflush(pd->driver, (void *) &v[index]);
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psb_mmu_clflush(pd->driver, (void *)&v[index]);
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atomic_set(&pd->driver->needs_tlbflush, 1);
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}
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}
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@ -420,8 +435,7 @@ static void psb_mmu_pt_unmap_unlock(struct psb_mmu_pt *pt)
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pd->tables[pt->index] = NULL;
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if (pd->hw_context != -1) {
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psb_mmu_clflush(pd->driver,
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(void *) &v[pt->index]);
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psb_mmu_clflush(pd->driver, (void *)&v[pt->index]);
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atomic_set(&pd->driver->needs_tlbflush, 1);
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}
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kunmap_atomic(pt->v);
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@ -432,8 +446,8 @@ static void psb_mmu_pt_unmap_unlock(struct psb_mmu_pt *pt)
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spin_unlock(&pd->driver->lock);
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}
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static inline void psb_mmu_set_pte(struct psb_mmu_pt *pt,
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unsigned long addr, uint32_t pte)
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static inline void psb_mmu_set_pte(struct psb_mmu_pt *pt, unsigned long addr,
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uint32_t pte)
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{
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pt->v[psb_mmu_pt_index(addr)] = pte;
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}
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@ -444,69 +458,50 @@ static inline void psb_mmu_invalidate_pte(struct psb_mmu_pt *pt,
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pt->v[psb_mmu_pt_index(addr)] = pt->pd->invalid_pte;
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}
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void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd,
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uint32_t mmu_offset, uint32_t gtt_start,
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uint32_t gtt_pages)
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{
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uint32_t *v;
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uint32_t start = psb_mmu_pd_index(mmu_offset);
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struct psb_mmu_driver *driver = pd->driver;
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int num_pages = gtt_pages;
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down_read(&driver->sem);
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spin_lock(&driver->lock);
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v = kmap_atomic(pd->p);
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v += start;
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while (gtt_pages--) {
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*v++ = gtt_start | pd->pd_mask;
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gtt_start += PAGE_SIZE;
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}
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/*ttm_tt_cache_flush(&pd->p, num_pages);*/
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psb_pages_clflush(pd->driver, &pd->p, num_pages);
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kunmap_atomic(v);
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spin_unlock(&driver->lock);
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if (pd->hw_context != -1)
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atomic_set(&pd->driver->needs_tlbflush, 1);
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up_read(&pd->driver->sem);
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psb_mmu_flush_pd(pd->driver, 0);
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}
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struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver *driver)
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{
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struct psb_mmu_pd *pd;
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/* down_read(&driver->sem); */
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down_read(&driver->sem);
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pd = driver->default_pd;
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/* up_read(&driver->sem); */
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up_read(&driver->sem);
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return pd;
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}
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/* Returns the physical address of the PD shared by sgx/msvdx */
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uint32_t psb_get_default_pd_addr(struct psb_mmu_driver *driver)
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{
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struct psb_mmu_pd *pd;
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pd = psb_mmu_get_default_pd(driver);
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return page_to_pfn(pd->p) << PAGE_SHIFT;
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}
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void psb_mmu_driver_takedown(struct psb_mmu_driver *driver)
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{
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struct drm_device *dev = driver->dev;
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struct drm_psb_private *dev_priv = dev->dev_private;
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PSB_WSGX32(driver->bif_ctrl, PSB_CR_BIF_CTRL);
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psb_mmu_free_pagedir(driver->default_pd);
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kfree(driver);
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}
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struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
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int trap_pagefaults,
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int invalid_type,
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struct drm_psb_private *dev_priv)
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struct psb_mmu_driver *psb_mmu_driver_init(struct drm_device *dev,
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int trap_pagefaults,
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int invalid_type,
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atomic_t *msvdx_mmu_invaldc)
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{
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struct psb_mmu_driver *driver;
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struct drm_psb_private *dev_priv = dev->dev_private;
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driver = kmalloc(sizeof(*driver), GFP_KERNEL);
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if (!driver)
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return NULL;
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driver->dev_priv = dev_priv;
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driver->dev = dev;
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driver->default_pd = psb_mmu_alloc_pd(driver, trap_pagefaults,
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invalid_type);
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if (!driver->default_pd)
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@ -515,17 +510,24 @@ struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
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spin_lock_init(&driver->lock);
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init_rwsem(&driver->sem);
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down_write(&driver->sem);
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driver->register_map = registers;
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atomic_set(&driver->needs_tlbflush, 1);
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driver->msvdx_mmu_invaldc = msvdx_mmu_invaldc;
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driver->bif_ctrl = PSB_RSGX32(PSB_CR_BIF_CTRL);
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PSB_WSGX32(driver->bif_ctrl | _PSB_CB_CTRL_CLEAR_FAULT,
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PSB_CR_BIF_CTRL);
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PSB_WSGX32(driver->bif_ctrl & ~_PSB_CB_CTRL_CLEAR_FAULT,
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PSB_CR_BIF_CTRL);
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driver->has_clflush = 0;
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#if defined(CONFIG_X86)
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if (boot_cpu_has(X86_FEATURE_CLFLSH)) {
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uint32_t tfms, misc, cap0, cap4, clflush_size;
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/*
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* clflush size is determined at kernel setup for x86_64
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* but not for i386. We have to do it here.
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* clflush size is determined at kernel setup for x86_64 but not
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* for i386. We have to do it here.
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*/
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cpuid(0x00000001, &tfms, &misc, &cap0, &cap4);
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@ -536,6 +538,7 @@ struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
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driver->clflush_mask = driver->clflush_add - 1;
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driver->clflush_mask = ~driver->clflush_mask;
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}
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#endif
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up_write(&driver->sem);
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return driver;
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@ -545,9 +548,9 @@ out_err1:
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return NULL;
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}
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static void psb_mmu_flush_ptes(struct psb_mmu_pd *pd,
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unsigned long address, uint32_t num_pages,
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uint32_t desired_tile_stride,
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#if defined(CONFIG_X86)
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static void psb_mmu_flush_ptes(struct psb_mmu_pd *pd, unsigned long address,
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uint32_t num_pages, uint32_t desired_tile_stride,
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uint32_t hw_tile_stride)
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{
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struct psb_mmu_pt *pt;
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@ -561,11 +564,8 @@ static void psb_mmu_flush_ptes(struct psb_mmu_pd *pd,
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unsigned long clflush_add = pd->driver->clflush_add;
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unsigned long clflush_mask = pd->driver->clflush_mask;
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if (!pd->driver->has_clflush) {
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/*ttm_tt_cache_flush(&pd->p, num_pages);*/
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psb_pages_clflush(pd->driver, &pd->p, num_pages);
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if (!pd->driver->has_clflush)
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return;
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}
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if (hw_tile_stride)
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rows = num_pages / desired_tile_stride;
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@ -586,10 +586,8 @@ static void psb_mmu_flush_ptes(struct psb_mmu_pd *pd,
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if (!pt)
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continue;
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do {
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psb_clflush(&pt->v
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[psb_mmu_pt_index(addr)]);
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} while (addr +=
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clflush_add,
|
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psb_clflush(&pt->v[psb_mmu_pt_index(addr)]);
|
||||
} while (addr += clflush_add,
|
||||
(addr & clflush_mask) < next);
|
||||
|
||||
psb_mmu_pt_unmap_unlock(pt);
|
||||
|
|
@ -598,6 +596,14 @@ static void psb_mmu_flush_ptes(struct psb_mmu_pd *pd,
|
|||
}
|
||||
mb();
|
||||
}
|
||||
#else
|
||||
static void psb_mmu_flush_ptes(struct psb_mmu_pd *pd, unsigned long address,
|
||||
uint32_t num_pages, uint32_t desired_tile_stride,
|
||||
uint32_t hw_tile_stride)
|
||||
{
|
||||
drm_ttm_cache_flush();
|
||||
}
|
||||
#endif
|
||||
|
||||
void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
|
||||
unsigned long address, uint32_t num_pages)
|
||||
|
|
@ -633,7 +639,7 @@ out:
|
|||
up_read(&pd->driver->sem);
|
||||
|
||||
if (pd->hw_context != -1)
|
||||
psb_mmu_flush(pd->driver, 0);
|
||||
psb_mmu_flush(pd->driver);
|
||||
|
||||
return;
|
||||
}
|
||||
|
|
@ -660,7 +666,7 @@ void psb_mmu_remove_pages(struct psb_mmu_pd *pd, unsigned long address,
|
|||
add = desired_tile_stride << PAGE_SHIFT;
|
||||
row_add = hw_tile_stride << PAGE_SHIFT;
|
||||
|
||||
/* down_read(&pd->driver->sem); */
|
||||
down_read(&pd->driver->sem);
|
||||
|
||||
/* Make sure we only need to flush this processor's cache */
|
||||
|
||||
|
|
@ -688,10 +694,10 @@ void psb_mmu_remove_pages(struct psb_mmu_pd *pd, unsigned long address,
|
|||
psb_mmu_flush_ptes(pd, f_address, num_pages,
|
||||
desired_tile_stride, hw_tile_stride);
|
||||
|
||||
/* up_read(&pd->driver->sem); */
|
||||
up_read(&pd->driver->sem);
|
||||
|
||||
if (pd->hw_context != -1)
|
||||
psb_mmu_flush(pd->driver, 0);
|
||||
psb_mmu_flush(pd->driver);
|
||||
}
|
||||
|
||||
int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd, uint32_t start_pfn,
|
||||
|
|
@ -704,7 +710,7 @@ int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd, uint32_t start_pfn,
|
|||
unsigned long end;
|
||||
unsigned long next;
|
||||
unsigned long f_address = address;
|
||||
int ret = 0;
|
||||
int ret = -ENOMEM;
|
||||
|
||||
down_read(&pd->driver->sem);
|
||||
|
||||
|
|
@ -726,6 +732,7 @@ int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd, uint32_t start_pfn,
|
|||
psb_mmu_pt_unmap_unlock(pt);
|
||||
|
||||
} while (addr = next, next != end);
|
||||
ret = 0;
|
||||
|
||||
out:
|
||||
if (pd->hw_context != -1)
|
||||
|
|
@ -734,15 +741,15 @@ out:
|
|||
up_read(&pd->driver->sem);
|
||||
|
||||
if (pd->hw_context != -1)
|
||||
psb_mmu_flush(pd->driver, 1);
|
||||
psb_mmu_flush(pd->driver);
|
||||
|
||||
return ret;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
|
||||
unsigned long address, uint32_t num_pages,
|
||||
uint32_t desired_tile_stride,
|
||||
uint32_t hw_tile_stride, int type)
|
||||
uint32_t desired_tile_stride, uint32_t hw_tile_stride,
|
||||
int type)
|
||||
{
|
||||
struct psb_mmu_pt *pt;
|
||||
uint32_t rows = 1;
|
||||
|
|
@ -754,7 +761,7 @@ int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
|
|||
unsigned long add;
|
||||
unsigned long row_add;
|
||||
unsigned long f_address = address;
|
||||
int ret = 0;
|
||||
int ret = -ENOMEM;
|
||||
|
||||
if (hw_tile_stride) {
|
||||
if (num_pages % desired_tile_stride != 0)
|
||||
|
|
@ -777,14 +784,11 @@ int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
|
|||
do {
|
||||
next = psb_pd_addr_end(addr, end);
|
||||
pt = psb_mmu_pt_alloc_map_lock(pd, addr);
|
||||
if (!pt) {
|
||||
ret = -ENOMEM;
|
||||
if (!pt)
|
||||
goto out;
|
||||
}
|
||||
do {
|
||||
pte =
|
||||
psb_mmu_mask_pte(page_to_pfn(*pages++),
|
||||
type);
|
||||
pte = psb_mmu_mask_pte(page_to_pfn(*pages++),
|
||||
type);
|
||||
psb_mmu_set_pte(pt, addr, pte);
|
||||
pt->count++;
|
||||
} while (addr += PAGE_SIZE, addr < next);
|
||||
|
|
@ -794,6 +798,8 @@ int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
|
|||
|
||||
address += row_add;
|
||||
}
|
||||
|
||||
ret = 0;
|
||||
out:
|
||||
if (pd->hw_context != -1)
|
||||
psb_mmu_flush_ptes(pd, f_address, num_pages,
|
||||
|
|
@ -802,7 +808,7 @@ out:
|
|||
up_read(&pd->driver->sem);
|
||||
|
||||
if (pd->hw_context != -1)
|
||||
psb_mmu_flush(pd->driver, 1);
|
||||
psb_mmu_flush(pd->driver);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -347,9 +347,7 @@ static int psb_driver_load(struct drm_device *dev, unsigned long chipset)
|
|||
if (ret)
|
||||
goto out_err;
|
||||
|
||||
dev_priv->mmu = psb_mmu_driver_init((void *)0,
|
||||
drm_psb_trap_pagefaults, 0,
|
||||
dev_priv);
|
||||
dev_priv->mmu = psb_mmu_driver_init(dev, drm_psb_trap_pagefaults, 0, 0);
|
||||
if (!dev_priv->mmu)
|
||||
goto out_err;
|
||||
|
||||
|
|
|
|||
|
|
@ -727,10 +727,10 @@ static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
|
|||
* MMU stuff.
|
||||
*/
|
||||
|
||||
extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
|
||||
int trap_pagefaults,
|
||||
int invalid_type,
|
||||
struct drm_psb_private *dev_priv);
|
||||
extern struct psb_mmu_driver *psb_mmu_driver_init(struct drm_device *dev,
|
||||
int trap_pagefaults,
|
||||
int invalid_type,
|
||||
atomic_t *msvdx_mmu_invaldc);
|
||||
extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
|
||||
extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver
|
||||
*driver);
|
||||
|
|
@ -740,7 +740,7 @@ extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
|
|||
int trap_pagefaults,
|
||||
int invalid_type);
|
||||
extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
|
||||
extern void psb_mmu_flush(struct psb_mmu_driver *driver, int rc_prot);
|
||||
extern void psb_mmu_flush(struct psb_mmu_driver *driver);
|
||||
extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
|
||||
unsigned long address,
|
||||
uint32_t num_pages);
|
||||
|
|
|
|||
Loading…
Reference in New Issue