i40evf: Use the correct defines to match the VF registers
Use CTLN1 instead of CTLN for the VF relative register space. Change-ID: Iefba63faf0307af55fec8dbb64f26059f7d91318 Signed-off-by: Anjali Singhai Jain <anjali.singhai@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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cd494fb4c2
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b1f3366b86
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@ -1293,17 +1293,17 @@ static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
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old_itr = q_vector->rx.itr;
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i40e_set_new_dynamic_itr(&q_vector->rx);
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if (old_itr != q_vector->rx.itr) {
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val = I40E_VFINT_DYN_CTLN_INTENA_MASK |
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I40E_VFINT_DYN_CTLN_CLEARPBA_MASK |
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val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
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I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
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(I40E_RX_ITR <<
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I40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT) |
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I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
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(q_vector->rx.itr <<
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I40E_VFINT_DYN_CTLN_INTERVAL_SHIFT);
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I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);
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} else {
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val = I40E_VFINT_DYN_CTLN_INTENA_MASK |
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I40E_VFINT_DYN_CTLN_CLEARPBA_MASK |
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val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
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I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
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(I40E_ITR_NONE <<
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I40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT);
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I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT);
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}
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if (!test_bit(__I40E_DOWN, &vsi->state))
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wr32(hw, I40E_VFINT_DYN_CTLN1(vector - 1), val);
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@ -1315,18 +1315,18 @@ static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
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old_itr = q_vector->tx.itr;
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i40e_set_new_dynamic_itr(&q_vector->tx);
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if (old_itr != q_vector->tx.itr) {
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val = I40E_VFINT_DYN_CTLN_INTENA_MASK |
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I40E_VFINT_DYN_CTLN_CLEARPBA_MASK |
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val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
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I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
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(I40E_TX_ITR <<
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I40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT) |
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I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
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(q_vector->tx.itr <<
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I40E_VFINT_DYN_CTLN_INTERVAL_SHIFT);
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I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);
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} else {
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val = I40E_VFINT_DYN_CTLN_INTENA_MASK |
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I40E_VFINT_DYN_CTLN_CLEARPBA_MASK |
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val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
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I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
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(I40E_ITR_NONE <<
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I40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT);
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I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT);
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}
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if (!test_bit(__I40E_DOWN, &vsi->state))
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wr32(hw, I40E_VFINT_DYN_CTLN1(vector - 1), val);
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@ -204,7 +204,7 @@ static void i40evf_misc_irq_enable(struct i40evf_adapter *adapter)
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wr32(hw, I40E_VFINT_DYN_CTL01, I40E_VFINT_DYN_CTL01_INTENA_MASK |
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I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
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wr32(hw, I40E_VFINT_ICR0_ENA1, I40E_VFINT_ICR0_ENA_ADMINQ_MASK);
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wr32(hw, I40E_VFINT_ICR0_ENA1, I40E_VFINT_ICR0_ENA1_ADMINQ_MASK);
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/* read flush */
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rd32(hw, I40E_VFGEN_RSTAT);
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@ -245,7 +245,7 @@ void i40evf_irq_enable_queues(struct i40evf_adapter *adapter, u32 mask)
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wr32(hw, I40E_VFINT_DYN_CTLN1(i - 1),
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I40E_VFINT_DYN_CTLN1_INTENA_MASK |
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I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK |
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I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);
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I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK);
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}
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}
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}
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@ -263,17 +263,17 @@ static void i40evf_fire_sw_int(struct i40evf_adapter *adapter, u32 mask)
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if (mask & 1) {
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dyn_ctl = rd32(hw, I40E_VFINT_DYN_CTL01);
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dyn_ctl |= I40E_VFINT_DYN_CTLN_SWINT_TRIG_MASK |
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dyn_ctl |= I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |
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I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK |
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I40E_VFINT_DYN_CTLN_CLEARPBA_MASK;
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I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK;
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wr32(hw, I40E_VFINT_DYN_CTL01, dyn_ctl);
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}
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for (i = 1; i < adapter->num_msix_vectors; i++) {
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if (mask & BIT(i)) {
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dyn_ctl = rd32(hw, I40E_VFINT_DYN_CTLN1(i - 1));
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dyn_ctl |= I40E_VFINT_DYN_CTLN_SWINT_TRIG_MASK |
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dyn_ctl |= I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |
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I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK |
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I40E_VFINT_DYN_CTLN_CLEARPBA_MASK;
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I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK;
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wr32(hw, I40E_VFINT_DYN_CTLN1(i - 1), dyn_ctl);
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}
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}
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@ -313,7 +313,7 @@ static irqreturn_t i40evf_msix_aq(int irq, void *data)
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val = rd32(hw, I40E_VFINT_DYN_CTL01);
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val = val | I40E_PFINT_DYN_CTL0_CLEARPBA_MASK;
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val = val | I40E_VFINT_DYN_CTL01_CLEARPBA_MASK;
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wr32(hw, I40E_VFINT_DYN_CTL01, val);
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/* schedule work on the private workqueue */
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@ -1779,34 +1779,34 @@ static void i40evf_adminq_task(struct work_struct *work)
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/* check for error indications */
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val = rd32(hw, hw->aq.arq.len);
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oldval = val;
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if (val & I40E_VF_ARQLEN_ARQVFE_MASK) {
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if (val & I40E_VF_ARQLEN1_ARQVFE_MASK) {
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dev_info(&adapter->pdev->dev, "ARQ VF Error detected\n");
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val &= ~I40E_VF_ARQLEN_ARQVFE_MASK;
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val &= ~I40E_VF_ARQLEN1_ARQVFE_MASK;
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}
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if (val & I40E_VF_ARQLEN_ARQOVFL_MASK) {
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if (val & I40E_VF_ARQLEN1_ARQOVFL_MASK) {
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dev_info(&adapter->pdev->dev, "ARQ Overflow Error detected\n");
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val &= ~I40E_VF_ARQLEN_ARQOVFL_MASK;
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val &= ~I40E_VF_ARQLEN1_ARQOVFL_MASK;
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}
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if (val & I40E_VF_ARQLEN_ARQCRIT_MASK) {
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if (val & I40E_VF_ARQLEN1_ARQCRIT_MASK) {
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dev_info(&adapter->pdev->dev, "ARQ Critical Error detected\n");
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val &= ~I40E_VF_ARQLEN_ARQCRIT_MASK;
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val &= ~I40E_VF_ARQLEN1_ARQCRIT_MASK;
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}
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if (oldval != val)
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wr32(hw, hw->aq.arq.len, val);
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val = rd32(hw, hw->aq.asq.len);
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oldval = val;
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if (val & I40E_VF_ATQLEN_ATQVFE_MASK) {
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if (val & I40E_VF_ATQLEN1_ATQVFE_MASK) {
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dev_info(&adapter->pdev->dev, "ASQ VF Error detected\n");
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val &= ~I40E_VF_ATQLEN_ATQVFE_MASK;
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val &= ~I40E_VF_ATQLEN1_ATQVFE_MASK;
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}
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if (val & I40E_VF_ATQLEN_ATQOVFL_MASK) {
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if (val & I40E_VF_ATQLEN1_ATQOVFL_MASK) {
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dev_info(&adapter->pdev->dev, "ASQ Overflow Error detected\n");
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val &= ~I40E_VF_ATQLEN_ATQOVFL_MASK;
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val &= ~I40E_VF_ATQLEN1_ATQOVFL_MASK;
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}
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if (val & I40E_VF_ATQLEN_ATQCRIT_MASK) {
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if (val & I40E_VF_ATQLEN1_ATQCRIT_MASK) {
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dev_info(&adapter->pdev->dev, "ASQ Critical Error detected\n");
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val &= ~I40E_VF_ATQLEN_ATQCRIT_MASK;
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val &= ~I40E_VF_ATQLEN1_ATQCRIT_MASK;
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}
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if (oldval != val)
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wr32(hw, hw->aq.asq.len, val);
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