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drm/nouveau/mpeg: cosmetic changes 

This is purely preparation for upcoming commits, there should be no
code changes here.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2015-08-20 14:54:08 +10:00
parent bfee3f3d97
commit b19de4f3d7
7 changed files with 155 additions and 167 deletions
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8
drivers/gpu/drm/nouveau/include/nvkm/engine/mpeg.h
View File

@ -24,17 +24,17 @@ struct nvkm_mpeg_chan {
#include <core/engine.h> #include <core/engine.h>
struct nvkm_mpeg { struct nvkm_mpeg {
struct nvkm_engine base; struct nvkm_engine engine;
}; };
#define nvkm_mpeg_create(p,e,c,d) \ #define nvkm_mpeg_create(p,e,c,d) \
nvkm_engine_create((p), (e), (c), true, "PMPEG", "mpeg", (d)) nvkm_engine_create((p), (e), (c), true, "PMPEG", "mpeg", (d))
#define nvkm_mpeg_destroy(d) \ #define nvkm_mpeg_destroy(d) \
nvkm_engine_destroy(&(d)->base) nvkm_engine_destroy(&(d)->engine)
#define nvkm_mpeg_init(d) \ #define nvkm_mpeg_init(d) \
nvkm_engine_init(&(d)->base) nvkm_engine_init(&(d)->engine)
#define nvkm_mpeg_fini(d,s) \ #define nvkm_mpeg_fini(d,s) \
nvkm_engine_fini(&(d)->base, (s)) nvkm_engine_fini(&(d)->engine, (s))
#define _nvkm_mpeg_dtor _nvkm_engine_dtor #define _nvkm_mpeg_dtor _nvkm_engine_dtor
#define _nvkm_mpeg_init _nvkm_engine_init #define _nvkm_mpeg_init _nvkm_engine_init

18
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/g84.c
View File

@ -23,10 +23,6 @@
*/ */
#include <engine/mpeg.h> #include <engine/mpeg.h>
struct g84_mpeg_priv {
struct nvkm_mpeg base;
};
struct g84_mpeg_chan { struct g84_mpeg_chan {
struct nvkm_mpeg_chan base; struct nvkm_mpeg_chan base;
}; };
@ -67,18 +63,18 @@ g84_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject) struct nvkm_object **pobject)
{ {
struct g84_mpeg_priv *priv; struct nvkm_mpeg *mpeg;
int ret; int ret;
ret = nvkm_mpeg_create(parent, engine, oclass, &priv); ret = nvkm_mpeg_create(parent, engine, oclass, &mpeg);
*pobject = nv_object(priv); *pobject = nv_object(mpeg);
if (ret) if (ret)
return ret; return ret;
nv_subdev(priv)->unit = 0x00000002; nv_subdev(mpeg)->unit = 0x00000002;
nv_subdev(priv)->intr = nv50_mpeg_intr; nv_subdev(mpeg)->intr = nv50_mpeg_intr;
nv_engine(priv)->cclass = &g84_mpeg_cclass; nv_engine(mpeg)->cclass = &g84_mpeg_cclass;
nv_engine(priv)->sclass = g84_mpeg_sclass; nv_engine(mpeg)->sclass = g84_mpeg_sclass;
return 0; return 0;
} }

112
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c
View File

@ -60,7 +60,7 @@ static int
nv31_mpeg_mthd_dma(struct nvkm_object *object, u32 mthd, void *arg, u32 len) nv31_mpeg_mthd_dma(struct nvkm_object *object, u32 mthd, void *arg, u32 len)
{ {
struct nvkm_instmem *imem = nvkm_instmem(object); struct nvkm_instmem *imem = nvkm_instmem(object);
struct nv31_mpeg_priv *priv = (void *)object->engine; struct nv31_mpeg *mpeg = (void *)object->engine;
u32 inst = *(u32 *)arg << 4; u32 inst = *(u32 *)arg << 4;
u32 dma0 = nv_ro32(imem, inst + 0); u32 dma0 = nv_ro32(imem, inst + 0);
u32 dma1 = nv_ro32(imem, inst + 4); u32 dma1 = nv_ro32(imem, inst + 4);
@ -74,22 +74,22 @@ nv31_mpeg_mthd_dma(struct nvkm_object *object, u32 mthd, void *arg, u32 len)
if (mthd == 0x0190) { if (mthd == 0x0190) {
/* DMA_CMD */ /* DMA_CMD */
nv_mask(priv, 0x00b300, 0x00010000, (dma0 & 0x00030000) ? 0x00010000 : 0); nv_mask(mpeg, 0x00b300, 0x00010000, (dma0 & 0x00030000) ? 0x00010000 : 0);
nv_wr32(priv, 0x00b334, base); nv_wr32(mpeg, 0x00b334, base);
nv_wr32(priv, 0x00b324, size); nv_wr32(mpeg, 0x00b324, size);
} else } else
if (mthd == 0x01a0) { if (mthd == 0x01a0) {
/* DMA_DATA */ /* DMA_DATA */
nv_mask(priv, 0x00b300, 0x00020000, (dma0 & 0x00030000) ? 0x00020000 : 0); nv_mask(mpeg, 0x00b300, 0x00020000, (dma0 & 0x00030000) ? 0x00020000 : 0);
nv_wr32(priv, 0x00b360, base); nv_wr32(mpeg, 0x00b360, base);
nv_wr32(priv, 0x00b364, size); nv_wr32(mpeg, 0x00b364, size);
} else { } else {
/* DMA_IMAGE, VRAM only */ /* DMA_IMAGE, VRAM only */
if (dma0 & 0x00030000) if (dma0 & 0x00030000)
return -EINVAL; return -EINVAL;
nv_wr32(priv, 0x00b370, base); nv_wr32(mpeg, 0x00b370, base);
nv_wr32(priv, 0x00b374, size); nv_wr32(mpeg, 0x00b374, size);
} }
return 0; return 0;
@ -129,7 +129,7 @@ nv31_mpeg_context_ctor(struct nvkm_object *parent,
struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject) struct nvkm_object **pobject)
{ {
struct nv31_mpeg_priv *priv = (void *)engine; struct nv31_mpeg *mpeg = (void *)engine;
struct nv31_mpeg_chan *chan; struct nv31_mpeg_chan *chan;
unsigned long flags; unsigned long flags;
int ret; int ret;
@ -139,28 +139,28 @@ nv31_mpeg_context_ctor(struct nvkm_object *parent,
if (ret) if (ret)
return ret; return ret;
spin_lock_irqsave(&nv_engine(priv)->lock, flags); spin_lock_irqsave(&nv_engine(mpeg)->lock, flags);
if (priv->chan) { if (mpeg->chan) {
spin_unlock_irqrestore(&nv_engine(priv)->lock, flags); spin_unlock_irqrestore(&nv_engine(mpeg)->lock, flags);
nvkm_object_destroy(&chan->base); nvkm_object_destroy(&chan->base);
*pobject = NULL; *pobject = NULL;
return -EBUSY; return -EBUSY;
} }
priv->chan = chan; mpeg->chan = chan;
spin_unlock_irqrestore(&nv_engine(priv)->lock, flags); spin_unlock_irqrestore(&nv_engine(mpeg)->lock, flags);
return 0; return 0;
} }
static void static void
nv31_mpeg_context_dtor(struct nvkm_object *object) nv31_mpeg_context_dtor(struct nvkm_object *object)
{ {
struct nv31_mpeg_priv *priv = (void *)object->engine; struct nv31_mpeg *mpeg = (void *)object->engine;
struct nv31_mpeg_chan *chan = (void *)object; struct nv31_mpeg_chan *chan = (void *)object;
unsigned long flags; unsigned long flags;
spin_lock_irqsave(&nv_engine(priv)->lock, flags); spin_lock_irqsave(&nv_engine(mpeg)->lock, flags);
priv->chan = NULL; mpeg->chan = NULL;
spin_unlock_irqrestore(&nv_engine(priv)->lock, flags); spin_unlock_irqrestore(&nv_engine(mpeg)->lock, flags);
nvkm_object_destroy(&chan->base); nvkm_object_destroy(&chan->base);
} }
@ -183,34 +183,34 @@ void
nv31_mpeg_tile_prog(struct nvkm_engine *engine, int i) nv31_mpeg_tile_prog(struct nvkm_engine *engine, int i)
{ {
struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i]; struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i];
struct nv31_mpeg_priv *priv = (void *)engine; struct nv31_mpeg *mpeg = (void *)engine;
nv_wr32(priv, 0x00b008 + (i * 0x10), tile->pitch); nv_wr32(mpeg, 0x00b008 + (i * 0x10), tile->pitch);
nv_wr32(priv, 0x00b004 + (i * 0x10), tile->limit); nv_wr32(mpeg, 0x00b004 + (i * 0x10), tile->limit);
nv_wr32(priv, 0x00b000 + (i * 0x10), tile->addr); nv_wr32(mpeg, 0x00b000 + (i * 0x10), tile->addr);
} }
void void
nv31_mpeg_intr(struct nvkm_subdev *subdev) nv31_mpeg_intr(struct nvkm_subdev *subdev)
{ {
struct nv31_mpeg_priv *priv = (void *)subdev; struct nv31_mpeg *mpeg = (void *)subdev;
struct nvkm_fifo *fifo = nvkm_fifo(subdev); struct nvkm_fifo *fifo = nvkm_fifo(subdev);
struct nvkm_handle *handle; struct nvkm_handle *handle;
struct nvkm_object *engctx; struct nvkm_object *engctx;
u32 stat = nv_rd32(priv, 0x00b100); u32 stat = nv_rd32(mpeg, 0x00b100);
u32 type = nv_rd32(priv, 0x00b230); u32 type = nv_rd32(mpeg, 0x00b230);
u32 mthd = nv_rd32(priv, 0x00b234); u32 mthd = nv_rd32(mpeg, 0x00b234);
u32 data = nv_rd32(priv, 0x00b238); u32 data = nv_rd32(mpeg, 0x00b238);
u32 show = stat; u32 show = stat;
unsigned long flags; unsigned long flags;
spin_lock_irqsave(&nv_engine(priv)->lock, flags); spin_lock_irqsave(&nv_engine(mpeg)->lock, flags);
engctx = nv_object(priv->chan); engctx = nv_object(mpeg->chan);
if (stat & 0x01000000) { if (stat & 0x01000000) {
/* happens on initial binding of the object */ /* happens on initial binding of the object */
if (type == 0x00000020 && mthd == 0x0000) { if (type == 0x00000020 && mthd == 0x0000) {
nv_mask(priv, 0x00b308, 0x00000000, 0x00000000); nv_mask(mpeg, 0x00b308, 0x00000000, 0x00000000);
show &= ~0x01000000; show &= ~0x01000000;
} }
@ -222,16 +222,16 @@ nv31_mpeg_intr(struct nvkm_subdev *subdev)
} }
} }
nv_wr32(priv, 0x00b100, stat); nv_wr32(mpeg, 0x00b100, stat);
nv_wr32(priv, 0x00b230, 0x00000001); nv_wr32(mpeg, 0x00b230, 0x00000001);
if (show) { if (show) {
nv_error(priv, "ch %d [%s] 0x%08x 0x%08x 0x%08x 0x%08x\n", nv_error(mpeg, "ch %d [%s] 0x%08x 0x%08x 0x%08x 0x%08x\n",
fifo->chid(fifo, engctx), fifo->chid(fifo, engctx),
nvkm_client_name(engctx), stat, type, mthd, data); nvkm_client_name(engctx), stat, type, mthd, data);
} }
spin_unlock_irqrestore(&nv_engine(priv)->lock, flags); spin_unlock_irqrestore(&nv_engine(mpeg)->lock, flags);
} }
static int static int
@ -239,19 +239,19 @@ nv31_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject) struct nvkm_object **pobject)
{ {
struct nv31_mpeg_priv *priv; struct nv31_mpeg *mpeg;
int ret; int ret;
ret = nvkm_mpeg_create(parent, engine, oclass, &priv); ret = nvkm_mpeg_create(parent, engine, oclass, &mpeg);
*pobject = nv_object(priv); *pobject = nv_object(mpeg);
if (ret) if (ret)
return ret; return ret;
nv_subdev(priv)->unit = 0x00000002; nv_subdev(mpeg)->unit = 0x00000002;
nv_subdev(priv)->intr = nv31_mpeg_intr; nv_subdev(mpeg)->intr = nv31_mpeg_intr;
nv_engine(priv)->cclass = &nv31_mpeg_cclass; nv_engine(mpeg)->cclass = &nv31_mpeg_cclass;
nv_engine(priv)->sclass = nv31_mpeg_sclass; nv_engine(mpeg)->sclass = nv31_mpeg_sclass;
nv_engine(priv)->tile_prog = nv31_mpeg_tile_prog; nv_engine(mpeg)->tile_prog = nv31_mpeg_tile_prog;
return 0; return 0;
} }
@ -259,33 +259,33 @@ int
nv31_mpeg_init(struct nvkm_object *object) nv31_mpeg_init(struct nvkm_object *object)
{ {
struct nvkm_engine *engine = nv_engine(object); struct nvkm_engine *engine = nv_engine(object);
struct nv31_mpeg_priv *priv = (void *)object; struct nv31_mpeg *mpeg = (void *)object;
struct nvkm_fb *fb = nvkm_fb(object); struct nvkm_fb *fb = nvkm_fb(object);
int ret, i; int ret, i;
ret = nvkm_mpeg_init(&priv->base); ret = nvkm_mpeg_init(&mpeg->base);
if (ret) if (ret)
return ret; return ret;
/* VPE init */ /* VPE init */
nv_wr32(priv, 0x00b0e0, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */ nv_wr32(mpeg, 0x00b0e0, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */
nv_wr32(priv, 0x00b0e8, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */ nv_wr32(mpeg, 0x00b0e8, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */
for (i = 0; i < fb->tile.regions; i++) for (i = 0; i < fb->tile.regions; i++)
engine->tile_prog(engine, i); engine->tile_prog(engine, i);
/* PMPEG init */ /* PMPEG init */
nv_wr32(priv, 0x00b32c, 0x00000000); nv_wr32(mpeg, 0x00b32c, 0x00000000);
nv_wr32(priv, 0x00b314, 0x00000100); nv_wr32(mpeg, 0x00b314, 0x00000100);
nv_wr32(priv, 0x00b220, 0x00000031); nv_wr32(mpeg, 0x00b220, 0x00000031);
nv_wr32(priv, 0x00b300, 0x02001ec1); nv_wr32(mpeg, 0x00b300, 0x02001ec1);
nv_mask(priv, 0x00b32c, 0x00000001, 0x00000001); nv_mask(mpeg, 0x00b32c, 0x00000001, 0x00000001);
nv_wr32(priv, 0x00b100, 0xffffffff); nv_wr32(mpeg, 0x00b100, 0xffffffff);
nv_wr32(priv, 0x00b140, 0xffffffff); nv_wr32(mpeg, 0x00b140, 0xffffffff);
if (!nv_wait(priv, 0x00b200, 0x00000001, 0x00000000)) { if (!nv_wait(mpeg, 0x00b200, 0x00000001, 0x00000000)) {
nv_error(priv, "timeout 0x%08x\n", nv_rd32(priv, 0x00b200)); nv_error(mpeg, "timeout 0x%08x\n", nv_rd32(mpeg, 0x00b200));
return -EBUSY; return -EBUSY;
} }

2
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.h
View File

@ -6,7 +6,7 @@ struct nv31_mpeg_chan {
struct nvkm_object base; struct nvkm_object base;
}; };
struct nv31_mpeg_priv { struct nv31_mpeg {
struct nvkm_mpeg base; struct nvkm_mpeg base;
struct nv31_mpeg_chan *chan; struct nv31_mpeg_chan *chan;
}; };

44
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c
View File

@ -33,7 +33,7 @@ static int
nv40_mpeg_mthd_dma(struct nvkm_object *object, u32 mthd, void *arg, u32 len) nv40_mpeg_mthd_dma(struct nvkm_object *object, u32 mthd, void *arg, u32 len)
{ {
struct nvkm_instmem *imem = nvkm_instmem(object); struct nvkm_instmem *imem = nvkm_instmem(object);
struct nv31_mpeg_priv *priv = (void *)object->engine; struct nv31_mpeg *mpeg = (void *)object->engine;
u32 inst = *(u32 *)arg << 4; u32 inst = *(u32 *)arg << 4;
u32 dma0 = nv_ro32(imem, inst + 0); u32 dma0 = nv_ro32(imem, inst + 0);
u32 dma1 = nv_ro32(imem, inst + 4); u32 dma1 = nv_ro32(imem, inst + 4);
@ -47,22 +47,22 @@ nv40_mpeg_mthd_dma(struct nvkm_object *object, u32 mthd, void *arg, u32 len)
if (mthd == 0x0190) { if (mthd == 0x0190) {
/* DMA_CMD */ /* DMA_CMD */
nv_mask(priv, 0x00b300, 0x00030000, (dma0 & 0x00030000)); nv_mask(mpeg, 0x00b300, 0x00030000, (dma0 & 0x00030000));
nv_wr32(priv, 0x00b334, base); nv_wr32(mpeg, 0x00b334, base);
nv_wr32(priv, 0x00b324, size); nv_wr32(mpeg, 0x00b324, size);
} else } else
if (mthd == 0x01a0) { if (mthd == 0x01a0) {
/* DMA_DATA */ /* DMA_DATA */
nv_mask(priv, 0x00b300, 0x000c0000, (dma0 & 0x00030000) << 2); nv_mask(mpeg, 0x00b300, 0x000c0000, (dma0 & 0x00030000) << 2);
nv_wr32(priv, 0x00b360, base); nv_wr32(mpeg, 0x00b360, base);
nv_wr32(priv, 0x00b364, size); nv_wr32(mpeg, 0x00b364, size);
} else { } else {
/* DMA_IMAGE, VRAM only */ /* DMA_IMAGE, VRAM only */
if (dma0 & 0x00030000) if (dma0 & 0x00030000)
return -EINVAL; return -EINVAL;
nv_wr32(priv, 0x00b370, base); nv_wr32(mpeg, 0x00b370, base);
nv_wr32(priv, 0x00b374, size); nv_wr32(mpeg, 0x00b374, size);
} }
return 0; return 0;
@ -89,15 +89,15 @@ nv40_mpeg_sclass[] = {
static void static void
nv40_mpeg_intr(struct nvkm_subdev *subdev) nv40_mpeg_intr(struct nvkm_subdev *subdev)
{ {
struct nv31_mpeg_priv *priv = (void *)subdev; struct nv31_mpeg *mpeg = (void *)subdev;
u32 stat; u32 stat;
if ((stat = nv_rd32(priv, 0x00b100))) if ((stat = nv_rd32(mpeg, 0x00b100)))
nv31_mpeg_intr(subdev); nv31_mpeg_intr(subdev);
if ((stat = nv_rd32(priv, 0x00b800))) { if ((stat = nv_rd32(mpeg, 0x00b800))) {
nv_error(priv, "PMSRCH 0x%08x\n", stat); nv_error(mpeg, "PMSRCH 0x%08x\n", stat);
nv_wr32(priv, 0x00b800, stat); nv_wr32(mpeg, 0x00b800, stat);
} }
} }
@ -106,19 +106,19 @@ nv40_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject) struct nvkm_object **pobject)
{ {
struct nv31_mpeg_priv *priv; struct nv31_mpeg *mpeg;
int ret; int ret;
ret = nvkm_mpeg_create(parent, engine, oclass, &priv); ret = nvkm_mpeg_create(parent, engine, oclass, &mpeg);
*pobject = nv_object(priv); *pobject = nv_object(mpeg);
if (ret) if (ret)
return ret; return ret;
nv_subdev(priv)->unit = 0x00000002; nv_subdev(mpeg)->unit = 0x00000002;
nv_subdev(priv)->intr = nv40_mpeg_intr; nv_subdev(mpeg)->intr = nv40_mpeg_intr;
nv_engine(priv)->cclass = &nv31_mpeg_cclass; nv_engine(mpeg)->cclass = &nv31_mpeg_cclass;
nv_engine(priv)->sclass = nv40_mpeg_sclass; nv_engine(mpeg)->sclass = nv40_mpeg_sclass;
nv_engine(priv)->tile_prog = nv31_mpeg_tile_prog; nv_engine(mpeg)->tile_prog = nv31_mpeg_tile_prog;
return 0; return 0;
} }

60
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c
View File

@ -27,10 +27,6 @@
#include <core/handle.h> #include <core/handle.h>
#include <engine/fifo.h> #include <engine/fifo.h>
struct nv44_mpeg_priv {
struct nvkm_mpeg base;
};
struct nv44_mpeg_chan { struct nv44_mpeg_chan {
struct nvkm_mpeg_chan base; struct nvkm_mpeg_chan base;
}; };
@ -62,14 +58,14 @@ static int
nv44_mpeg_context_fini(struct nvkm_object *object, bool suspend) nv44_mpeg_context_fini(struct nvkm_object *object, bool suspend)
{ {
struct nv44_mpeg_priv *priv = (void *)object->engine; struct nvkm_mpeg *mpeg = (void *)object->engine;
struct nv44_mpeg_chan *chan = (void *)object; struct nv44_mpeg_chan *chan = (void *)object;
u32 inst = 0x80000000 | nv_gpuobj(chan)->addr >> 4; u32 inst = 0x80000000 | nv_gpuobj(chan)->addr >> 4;
nv_mask(priv, 0x00b32c, 0x00000001, 0x00000000); nv_mask(mpeg, 0x00b32c, 0x00000001, 0x00000000);
if (nv_rd32(priv, 0x00b318) == inst) if (nv_rd32(mpeg, 0x00b318) == inst)
nv_mask(priv, 0x00b318, 0x80000000, 0x00000000); nv_mask(mpeg, 0x00b318, 0x80000000, 0x00000000);
nv_mask(priv, 0x00b32c, 0x00000001, 0x00000001); nv_mask(mpeg, 0x00b32c, 0x00000001, 0x00000001);
return 0; return 0;
} }
@ -97,12 +93,12 @@ nv44_mpeg_intr(struct nvkm_subdev *subdev)
struct nvkm_engine *engine = nv_engine(subdev); struct nvkm_engine *engine = nv_engine(subdev);
struct nvkm_object *engctx; struct nvkm_object *engctx;
struct nvkm_handle *handle; struct nvkm_handle *handle;
struct nv44_mpeg_priv *priv = (void *)subdev; struct nvkm_mpeg *mpeg = (void *)subdev;
u32 inst = nv_rd32(priv, 0x00b318) & 0x000fffff; u32 inst = nv_rd32(mpeg, 0x00b318) & 0x000fffff;
u32 stat = nv_rd32(priv, 0x00b100); u32 stat = nv_rd32(mpeg, 0x00b100);
u32 type = nv_rd32(priv, 0x00b230); u32 type = nv_rd32(mpeg, 0x00b230);
u32 mthd = nv_rd32(priv, 0x00b234); u32 mthd = nv_rd32(mpeg, 0x00b234);
u32 data = nv_rd32(priv, 0x00b238); u32 data = nv_rd32(mpeg, 0x00b238);
u32 show = stat; u32 show = stat;
int chid; int chid;
@ -112,7 +108,7 @@ nv44_mpeg_intr(struct nvkm_subdev *subdev)
if (stat & 0x01000000) { if (stat & 0x01000000) {
/* happens on initial binding of the object */ /* happens on initial binding of the object */
if (type == 0x00000020 && mthd == 0x0000) { if (type == 0x00000020 && mthd == 0x0000) {
nv_mask(priv, 0x00b308, 0x00000000, 0x00000000); nv_mask(mpeg, 0x00b308, 0x00000000, 0x00000000);
show &= ~0x01000000; show &= ~0x01000000;
} }
@ -124,11 +120,11 @@ nv44_mpeg_intr(struct nvkm_subdev *subdev)
} }
} }
nv_wr32(priv, 0x00b100, stat); nv_wr32(mpeg, 0x00b100, stat);
nv_wr32(priv, 0x00b230, 0x00000001); nv_wr32(mpeg, 0x00b230, 0x00000001);
if (show) { if (show) {
nv_error(priv, nv_error(mpeg,
"ch %d [0x%08x %s] 0x%08x 0x%08x 0x%08x 0x%08x\n", "ch %d [0x%08x %s] 0x%08x 0x%08x 0x%08x 0x%08x\n",
chid, inst << 4, nvkm_client_name(engctx), stat, chid, inst << 4, nvkm_client_name(engctx), stat,
type, mthd, data); type, mthd, data);
@ -140,15 +136,15 @@ nv44_mpeg_intr(struct nvkm_subdev *subdev)
static void static void
nv44_mpeg_me_intr(struct nvkm_subdev *subdev) nv44_mpeg_me_intr(struct nvkm_subdev *subdev)
{ {
struct nv44_mpeg_priv *priv = (void *)subdev; struct nvkm_mpeg *mpeg = (void *)subdev;
u32 stat; u32 stat;
if ((stat = nv_rd32(priv, 0x00b100))) if ((stat = nv_rd32(mpeg, 0x00b100)))
nv44_mpeg_intr(subdev); nv44_mpeg_intr(subdev);
if ((stat = nv_rd32(priv, 0x00b800))) { if ((stat = nv_rd32(mpeg, 0x00b800))) {
nv_error(priv, "PMSRCH 0x%08x\n", stat); nv_error(mpeg, "PMSRCH 0x%08x\n", stat);
nv_wr32(priv, 0x00b800, stat); nv_wr32(mpeg, 0x00b800, stat);
} }
} }
@ -157,19 +153,19 @@ nv44_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject) struct nvkm_object **pobject)
{ {
struct nv44_mpeg_priv *priv; struct nvkm_mpeg *mpeg;
int ret; int ret;
ret = nvkm_mpeg_create(parent, engine, oclass, &priv); ret = nvkm_mpeg_create(parent, engine, oclass, &mpeg);
*pobject = nv_object(priv); *pobject = nv_object(mpeg);
if (ret) if (ret)
return ret; return ret;
nv_subdev(priv)->unit = 0x00000002; nv_subdev(mpeg)->unit = 0x00000002;
nv_subdev(priv)->intr = nv44_mpeg_me_intr; nv_subdev(mpeg)->intr = nv44_mpeg_me_intr;
nv_engine(priv)->cclass = &nv44_mpeg_cclass; nv_engine(mpeg)->cclass = &nv44_mpeg_cclass;
nv_engine(priv)->sclass = nv40_mpeg_sclass; nv_engine(mpeg)->sclass = nv40_mpeg_sclass;
nv_engine(priv)->tile_prog = nv31_mpeg_tile_prog; nv_engine(mpeg)->tile_prog = nv31_mpeg_tile_prog;
return 0; return 0;
} }

78
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c
View File

@ -26,10 +26,6 @@
#include <subdev/bar.h> #include <subdev/bar.h>
#include <subdev/timer.h> #include <subdev/timer.h>
struct nv50_mpeg_priv {
struct nvkm_mpeg base;
};
struct nv50_mpeg_chan { struct nv50_mpeg_chan {
struct nvkm_mpeg_chan base; struct nvkm_mpeg_chan base;
}; };
@ -122,42 +118,42 @@ nv50_mpeg_cclass = {
void void
nv50_mpeg_intr(struct nvkm_subdev *subdev) nv50_mpeg_intr(struct nvkm_subdev *subdev)
{ {
struct nv50_mpeg_priv *priv = (void *)subdev; struct nvkm_mpeg *mpeg = (void *)subdev;
u32 stat = nv_rd32(priv, 0x00b100); u32 stat = nv_rd32(mpeg, 0x00b100);
u32 type = nv_rd32(priv, 0x00b230); u32 type = nv_rd32(mpeg, 0x00b230);
u32 mthd = nv_rd32(priv, 0x00b234); u32 mthd = nv_rd32(mpeg, 0x00b234);
u32 data = nv_rd32(priv, 0x00b238); u32 data = nv_rd32(mpeg, 0x00b238);
u32 show = stat; u32 show = stat;
if (stat & 0x01000000) { if (stat & 0x01000000) {
/* happens on initial binding of the object */ /* happens on initial binding of the object */
if (type == 0x00000020 && mthd == 0x0000) { if (type == 0x00000020 && mthd == 0x0000) {
nv_wr32(priv, 0x00b308, 0x00000100); nv_wr32(mpeg, 0x00b308, 0x00000100);
show &= ~0x01000000; show &= ~0x01000000;
} }
} }
if (show) { if (show) {
nv_info(priv, "0x%08x 0x%08x 0x%08x 0x%08x\n", nv_info(mpeg, "0x%08x 0x%08x 0x%08x 0x%08x\n",
stat, type, mthd, data); stat, type, mthd, data);
} }
nv_wr32(priv, 0x00b100, stat); nv_wr32(mpeg, 0x00b100, stat);
nv_wr32(priv, 0x00b230, 0x00000001); nv_wr32(mpeg, 0x00b230, 0x00000001);
} }
static void static void
nv50_vpe_intr(struct nvkm_subdev *subdev) nv50_vpe_intr(struct nvkm_subdev *subdev)
{ {
struct nv50_mpeg_priv *priv = (void *)subdev; struct nvkm_mpeg *mpeg = (void *)subdev;
if (nv_rd32(priv, 0x00b100)) if (nv_rd32(mpeg, 0x00b100))
nv50_mpeg_intr(subdev); nv50_mpeg_intr(subdev);
if (nv_rd32(priv, 0x00b800)) { if (nv_rd32(mpeg, 0x00b800)) {
u32 stat = nv_rd32(priv, 0x00b800); u32 stat = nv_rd32(mpeg, 0x00b800);
nv_info(priv, "PMSRCH: 0x%08x\n", stat); nv_info(mpeg, "PMSRCH: 0x%08x\n", stat);
nv_wr32(priv, 0xb800, stat); nv_wr32(mpeg, 0xb800, stat);
} }
} }
@ -166,47 +162,47 @@ nv50_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject) struct nvkm_object **pobject)
{ {
struct nv50_mpeg_priv *priv; struct nvkm_mpeg *mpeg;
int ret; int ret;
ret = nvkm_mpeg_create(parent, engine, oclass, &priv); ret = nvkm_mpeg_create(parent, engine, oclass, &mpeg);
*pobject = nv_object(priv); *pobject = nv_object(mpeg);
if (ret) if (ret)
return ret; return ret;
nv_subdev(priv)->unit = 0x00400002; nv_subdev(mpeg)->unit = 0x00400002;
nv_subdev(priv)->intr = nv50_vpe_intr; nv_subdev(mpeg)->intr = nv50_vpe_intr;
nv_engine(priv)->cclass = &nv50_mpeg_cclass; nv_engine(mpeg)->cclass = &nv50_mpeg_cclass;
nv_engine(priv)->sclass = nv50_mpeg_sclass; nv_engine(mpeg)->sclass = nv50_mpeg_sclass;
return 0; return 0;
} }
int int
nv50_mpeg_init(struct nvkm_object *object) nv50_mpeg_init(struct nvkm_object *object)
{ {
struct nv50_mpeg_priv *priv = (void *)object; struct nvkm_mpeg *mpeg = (void *)object;
int ret; int ret;
ret = nvkm_mpeg_init(&priv->base); ret = nvkm_mpeg_init(mpeg);
if (ret) if (ret)
return ret; return ret;
nv_wr32(priv, 0x00b32c, 0x00000000); nv_wr32(mpeg, 0x00b32c, 0x00000000);
nv_wr32(priv, 0x00b314, 0x00000100); nv_wr32(mpeg, 0x00b314, 0x00000100);
nv_wr32(priv, 0x00b0e0, 0x0000001a); nv_wr32(mpeg, 0x00b0e0, 0x0000001a);
nv_wr32(priv, 0x00b220, 0x00000044); nv_wr32(mpeg, 0x00b220, 0x00000044);
nv_wr32(priv, 0x00b300, 0x00801ec1); nv_wr32(mpeg, 0x00b300, 0x00801ec1);
nv_wr32(priv, 0x00b390, 0x00000000); nv_wr32(mpeg, 0x00b390, 0x00000000);
nv_wr32(priv, 0x00b394, 0x00000000); nv_wr32(mpeg, 0x00b394, 0x00000000);
nv_wr32(priv, 0x00b398, 0x00000000); nv_wr32(mpeg, 0x00b398, 0x00000000);
nv_mask(priv, 0x00b32c, 0x00000001, 0x00000001); nv_mask(mpeg, 0x00b32c, 0x00000001, 0x00000001);
nv_wr32(priv, 0x00b100, 0xffffffff); nv_wr32(mpeg, 0x00b100, 0xffffffff);
nv_wr32(priv, 0x00b140, 0xffffffff); nv_wr32(mpeg, 0x00b140, 0xffffffff);
if (!nv_wait(priv, 0x00b200, 0x00000001, 0x00000000)) { if (!nv_wait(mpeg, 0x00b200, 0x00000001, 0x00000000)) {
nv_error(priv, "timeout 0x%08x\n", nv_rd32(priv, 0x00b200)); nv_error(mpeg, "timeout 0x%08x\n", nv_rd32(mpeg, 0x00b200));
return -EBUSY; return -EBUSY;
} }