drm/nouveau/mpeg: cosmetic changes
This is purely preparation for upcoming commits, there should be no code changes here. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
bfee3f3d97
commit
b19de4f3d7
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@ -24,17 +24,17 @@ struct nvkm_mpeg_chan {
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#include <core/engine.h>
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struct nvkm_mpeg {
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struct nvkm_engine base;
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struct nvkm_engine engine;
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};
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#define nvkm_mpeg_create(p,e,c,d) \
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nvkm_engine_create((p), (e), (c), true, "PMPEG", "mpeg", (d))
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#define nvkm_mpeg_destroy(d) \
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nvkm_engine_destroy(&(d)->base)
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nvkm_engine_destroy(&(d)->engine)
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#define nvkm_mpeg_init(d) \
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nvkm_engine_init(&(d)->base)
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nvkm_engine_init(&(d)->engine)
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#define nvkm_mpeg_fini(d,s) \
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nvkm_engine_fini(&(d)->base, (s))
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nvkm_engine_fini(&(d)->engine, (s))
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#define _nvkm_mpeg_dtor _nvkm_engine_dtor
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#define _nvkm_mpeg_init _nvkm_engine_init
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@ -23,10 +23,6 @@
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*/
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#include <engine/mpeg.h>
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struct g84_mpeg_priv {
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struct nvkm_mpeg base;
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};
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struct g84_mpeg_chan {
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struct nvkm_mpeg_chan base;
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};
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@ -67,18 +63,18 @@ g84_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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{
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struct g84_mpeg_priv *priv;
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struct nvkm_mpeg *mpeg;
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int ret;
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ret = nvkm_mpeg_create(parent, engine, oclass, &priv);
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*pobject = nv_object(priv);
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ret = nvkm_mpeg_create(parent, engine, oclass, &mpeg);
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*pobject = nv_object(mpeg);
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if (ret)
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return ret;
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nv_subdev(priv)->unit = 0x00000002;
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nv_subdev(priv)->intr = nv50_mpeg_intr;
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nv_engine(priv)->cclass = &g84_mpeg_cclass;
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nv_engine(priv)->sclass = g84_mpeg_sclass;
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nv_subdev(mpeg)->unit = 0x00000002;
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nv_subdev(mpeg)->intr = nv50_mpeg_intr;
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nv_engine(mpeg)->cclass = &g84_mpeg_cclass;
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nv_engine(mpeg)->sclass = g84_mpeg_sclass;
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return 0;
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}
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@ -60,7 +60,7 @@ static int
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nv31_mpeg_mthd_dma(struct nvkm_object *object, u32 mthd, void *arg, u32 len)
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{
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struct nvkm_instmem *imem = nvkm_instmem(object);
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struct nv31_mpeg_priv *priv = (void *)object->engine;
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struct nv31_mpeg *mpeg = (void *)object->engine;
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u32 inst = *(u32 *)arg << 4;
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u32 dma0 = nv_ro32(imem, inst + 0);
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u32 dma1 = nv_ro32(imem, inst + 4);
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@ -74,22 +74,22 @@ nv31_mpeg_mthd_dma(struct nvkm_object *object, u32 mthd, void *arg, u32 len)
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if (mthd == 0x0190) {
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/* DMA_CMD */
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nv_mask(priv, 0x00b300, 0x00010000, (dma0 & 0x00030000) ? 0x00010000 : 0);
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nv_wr32(priv, 0x00b334, base);
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nv_wr32(priv, 0x00b324, size);
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nv_mask(mpeg, 0x00b300, 0x00010000, (dma0 & 0x00030000) ? 0x00010000 : 0);
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nv_wr32(mpeg, 0x00b334, base);
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nv_wr32(mpeg, 0x00b324, size);
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} else
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if (mthd == 0x01a0) {
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/* DMA_DATA */
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nv_mask(priv, 0x00b300, 0x00020000, (dma0 & 0x00030000) ? 0x00020000 : 0);
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nv_wr32(priv, 0x00b360, base);
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nv_wr32(priv, 0x00b364, size);
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nv_mask(mpeg, 0x00b300, 0x00020000, (dma0 & 0x00030000) ? 0x00020000 : 0);
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nv_wr32(mpeg, 0x00b360, base);
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nv_wr32(mpeg, 0x00b364, size);
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} else {
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/* DMA_IMAGE, VRAM only */
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if (dma0 & 0x00030000)
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return -EINVAL;
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nv_wr32(priv, 0x00b370, base);
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nv_wr32(priv, 0x00b374, size);
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nv_wr32(mpeg, 0x00b370, base);
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nv_wr32(mpeg, 0x00b374, size);
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}
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return 0;
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@ -129,7 +129,7 @@ nv31_mpeg_context_ctor(struct nvkm_object *parent,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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{
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struct nv31_mpeg_priv *priv = (void *)engine;
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struct nv31_mpeg *mpeg = (void *)engine;
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struct nv31_mpeg_chan *chan;
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unsigned long flags;
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int ret;
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@ -139,28 +139,28 @@ nv31_mpeg_context_ctor(struct nvkm_object *parent,
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if (ret)
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return ret;
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spin_lock_irqsave(&nv_engine(priv)->lock, flags);
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if (priv->chan) {
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spin_unlock_irqrestore(&nv_engine(priv)->lock, flags);
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spin_lock_irqsave(&nv_engine(mpeg)->lock, flags);
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if (mpeg->chan) {
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spin_unlock_irqrestore(&nv_engine(mpeg)->lock, flags);
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nvkm_object_destroy(&chan->base);
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*pobject = NULL;
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return -EBUSY;
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}
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priv->chan = chan;
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spin_unlock_irqrestore(&nv_engine(priv)->lock, flags);
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mpeg->chan = chan;
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spin_unlock_irqrestore(&nv_engine(mpeg)->lock, flags);
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return 0;
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}
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static void
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nv31_mpeg_context_dtor(struct nvkm_object *object)
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{
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struct nv31_mpeg_priv *priv = (void *)object->engine;
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struct nv31_mpeg *mpeg = (void *)object->engine;
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struct nv31_mpeg_chan *chan = (void *)object;
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unsigned long flags;
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spin_lock_irqsave(&nv_engine(priv)->lock, flags);
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priv->chan = NULL;
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spin_unlock_irqrestore(&nv_engine(priv)->lock, flags);
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spin_lock_irqsave(&nv_engine(mpeg)->lock, flags);
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mpeg->chan = NULL;
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spin_unlock_irqrestore(&nv_engine(mpeg)->lock, flags);
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nvkm_object_destroy(&chan->base);
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}
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@ -183,34 +183,34 @@ void
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nv31_mpeg_tile_prog(struct nvkm_engine *engine, int i)
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{
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struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i];
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struct nv31_mpeg_priv *priv = (void *)engine;
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struct nv31_mpeg *mpeg = (void *)engine;
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nv_wr32(priv, 0x00b008 + (i * 0x10), tile->pitch);
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nv_wr32(priv, 0x00b004 + (i * 0x10), tile->limit);
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nv_wr32(priv, 0x00b000 + (i * 0x10), tile->addr);
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nv_wr32(mpeg, 0x00b008 + (i * 0x10), tile->pitch);
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nv_wr32(mpeg, 0x00b004 + (i * 0x10), tile->limit);
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nv_wr32(mpeg, 0x00b000 + (i * 0x10), tile->addr);
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}
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void
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nv31_mpeg_intr(struct nvkm_subdev *subdev)
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{
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struct nv31_mpeg_priv *priv = (void *)subdev;
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struct nv31_mpeg *mpeg = (void *)subdev;
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struct nvkm_fifo *fifo = nvkm_fifo(subdev);
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struct nvkm_handle *handle;
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struct nvkm_object *engctx;
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u32 stat = nv_rd32(priv, 0x00b100);
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u32 type = nv_rd32(priv, 0x00b230);
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u32 mthd = nv_rd32(priv, 0x00b234);
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u32 data = nv_rd32(priv, 0x00b238);
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u32 stat = nv_rd32(mpeg, 0x00b100);
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u32 type = nv_rd32(mpeg, 0x00b230);
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u32 mthd = nv_rd32(mpeg, 0x00b234);
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u32 data = nv_rd32(mpeg, 0x00b238);
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u32 show = stat;
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unsigned long flags;
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spin_lock_irqsave(&nv_engine(priv)->lock, flags);
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engctx = nv_object(priv->chan);
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spin_lock_irqsave(&nv_engine(mpeg)->lock, flags);
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engctx = nv_object(mpeg->chan);
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if (stat & 0x01000000) {
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/* happens on initial binding of the object */
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if (type == 0x00000020 && mthd == 0x0000) {
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nv_mask(priv, 0x00b308, 0x00000000, 0x00000000);
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nv_mask(mpeg, 0x00b308, 0x00000000, 0x00000000);
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show &= ~0x01000000;
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}
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@ -222,16 +222,16 @@ nv31_mpeg_intr(struct nvkm_subdev *subdev)
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}
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}
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nv_wr32(priv, 0x00b100, stat);
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nv_wr32(priv, 0x00b230, 0x00000001);
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nv_wr32(mpeg, 0x00b100, stat);
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nv_wr32(mpeg, 0x00b230, 0x00000001);
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if (show) {
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nv_error(priv, "ch %d [%s] 0x%08x 0x%08x 0x%08x 0x%08x\n",
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nv_error(mpeg, "ch %d [%s] 0x%08x 0x%08x 0x%08x 0x%08x\n",
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fifo->chid(fifo, engctx),
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nvkm_client_name(engctx), stat, type, mthd, data);
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}
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spin_unlock_irqrestore(&nv_engine(priv)->lock, flags);
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spin_unlock_irqrestore(&nv_engine(mpeg)->lock, flags);
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}
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static int
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@ -239,19 +239,19 @@ nv31_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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{
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struct nv31_mpeg_priv *priv;
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struct nv31_mpeg *mpeg;
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int ret;
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ret = nvkm_mpeg_create(parent, engine, oclass, &priv);
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*pobject = nv_object(priv);
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ret = nvkm_mpeg_create(parent, engine, oclass, &mpeg);
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*pobject = nv_object(mpeg);
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if (ret)
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return ret;
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nv_subdev(priv)->unit = 0x00000002;
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nv_subdev(priv)->intr = nv31_mpeg_intr;
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nv_engine(priv)->cclass = &nv31_mpeg_cclass;
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nv_engine(priv)->sclass = nv31_mpeg_sclass;
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nv_engine(priv)->tile_prog = nv31_mpeg_tile_prog;
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nv_subdev(mpeg)->unit = 0x00000002;
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nv_subdev(mpeg)->intr = nv31_mpeg_intr;
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nv_engine(mpeg)->cclass = &nv31_mpeg_cclass;
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nv_engine(mpeg)->sclass = nv31_mpeg_sclass;
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nv_engine(mpeg)->tile_prog = nv31_mpeg_tile_prog;
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return 0;
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}
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@ -259,33 +259,33 @@ int
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nv31_mpeg_init(struct nvkm_object *object)
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{
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struct nvkm_engine *engine = nv_engine(object);
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struct nv31_mpeg_priv *priv = (void *)object;
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struct nv31_mpeg *mpeg = (void *)object;
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struct nvkm_fb *fb = nvkm_fb(object);
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int ret, i;
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ret = nvkm_mpeg_init(&priv->base);
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ret = nvkm_mpeg_init(&mpeg->base);
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if (ret)
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return ret;
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/* VPE init */
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nv_wr32(priv, 0x00b0e0, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */
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nv_wr32(priv, 0x00b0e8, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */
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nv_wr32(mpeg, 0x00b0e0, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */
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nv_wr32(mpeg, 0x00b0e8, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */
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for (i = 0; i < fb->tile.regions; i++)
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engine->tile_prog(engine, i);
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/* PMPEG init */
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nv_wr32(priv, 0x00b32c, 0x00000000);
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nv_wr32(priv, 0x00b314, 0x00000100);
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nv_wr32(priv, 0x00b220, 0x00000031);
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nv_wr32(priv, 0x00b300, 0x02001ec1);
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nv_mask(priv, 0x00b32c, 0x00000001, 0x00000001);
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nv_wr32(mpeg, 0x00b32c, 0x00000000);
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nv_wr32(mpeg, 0x00b314, 0x00000100);
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nv_wr32(mpeg, 0x00b220, 0x00000031);
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nv_wr32(mpeg, 0x00b300, 0x02001ec1);
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nv_mask(mpeg, 0x00b32c, 0x00000001, 0x00000001);
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nv_wr32(priv, 0x00b100, 0xffffffff);
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nv_wr32(priv, 0x00b140, 0xffffffff);
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nv_wr32(mpeg, 0x00b100, 0xffffffff);
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nv_wr32(mpeg, 0x00b140, 0xffffffff);
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if (!nv_wait(priv, 0x00b200, 0x00000001, 0x00000000)) {
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nv_error(priv, "timeout 0x%08x\n", nv_rd32(priv, 0x00b200));
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if (!nv_wait(mpeg, 0x00b200, 0x00000001, 0x00000000)) {
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nv_error(mpeg, "timeout 0x%08x\n", nv_rd32(mpeg, 0x00b200));
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return -EBUSY;
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}
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@ -6,7 +6,7 @@ struct nv31_mpeg_chan {
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struct nvkm_object base;
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};
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struct nv31_mpeg_priv {
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struct nv31_mpeg {
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struct nvkm_mpeg base;
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struct nv31_mpeg_chan *chan;
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};
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@ -33,7 +33,7 @@ static int
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nv40_mpeg_mthd_dma(struct nvkm_object *object, u32 mthd, void *arg, u32 len)
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{
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struct nvkm_instmem *imem = nvkm_instmem(object);
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struct nv31_mpeg_priv *priv = (void *)object->engine;
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struct nv31_mpeg *mpeg = (void *)object->engine;
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u32 inst = *(u32 *)arg << 4;
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u32 dma0 = nv_ro32(imem, inst + 0);
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u32 dma1 = nv_ro32(imem, inst + 4);
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@ -47,22 +47,22 @@ nv40_mpeg_mthd_dma(struct nvkm_object *object, u32 mthd, void *arg, u32 len)
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if (mthd == 0x0190) {
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/* DMA_CMD */
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nv_mask(priv, 0x00b300, 0x00030000, (dma0 & 0x00030000));
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nv_wr32(priv, 0x00b334, base);
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nv_wr32(priv, 0x00b324, size);
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nv_mask(mpeg, 0x00b300, 0x00030000, (dma0 & 0x00030000));
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nv_wr32(mpeg, 0x00b334, base);
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nv_wr32(mpeg, 0x00b324, size);
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} else
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if (mthd == 0x01a0) {
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/* DMA_DATA */
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nv_mask(priv, 0x00b300, 0x000c0000, (dma0 & 0x00030000) << 2);
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nv_wr32(priv, 0x00b360, base);
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nv_wr32(priv, 0x00b364, size);
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nv_mask(mpeg, 0x00b300, 0x000c0000, (dma0 & 0x00030000) << 2);
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nv_wr32(mpeg, 0x00b360, base);
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nv_wr32(mpeg, 0x00b364, size);
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} else {
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/* DMA_IMAGE, VRAM only */
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if (dma0 & 0x00030000)
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return -EINVAL;
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nv_wr32(priv, 0x00b370, base);
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nv_wr32(priv, 0x00b374, size);
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nv_wr32(mpeg, 0x00b370, base);
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nv_wr32(mpeg, 0x00b374, size);
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}
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return 0;
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@ -89,15 +89,15 @@ nv40_mpeg_sclass[] = {
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static void
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nv40_mpeg_intr(struct nvkm_subdev *subdev)
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{
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struct nv31_mpeg_priv *priv = (void *)subdev;
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struct nv31_mpeg *mpeg = (void *)subdev;
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u32 stat;
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if ((stat = nv_rd32(priv, 0x00b100)))
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if ((stat = nv_rd32(mpeg, 0x00b100)))
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nv31_mpeg_intr(subdev);
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if ((stat = nv_rd32(priv, 0x00b800))) {
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nv_error(priv, "PMSRCH 0x%08x\n", stat);
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nv_wr32(priv, 0x00b800, stat);
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if ((stat = nv_rd32(mpeg, 0x00b800))) {
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nv_error(mpeg, "PMSRCH 0x%08x\n", stat);
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nv_wr32(mpeg, 0x00b800, stat);
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}
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}
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@ -106,19 +106,19 @@ nv40_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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{
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struct nv31_mpeg_priv *priv;
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struct nv31_mpeg *mpeg;
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int ret;
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ret = nvkm_mpeg_create(parent, engine, oclass, &priv);
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*pobject = nv_object(priv);
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ret = nvkm_mpeg_create(parent, engine, oclass, &mpeg);
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*pobject = nv_object(mpeg);
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if (ret)
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return ret;
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nv_subdev(priv)->unit = 0x00000002;
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nv_subdev(priv)->intr = nv40_mpeg_intr;
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nv_engine(priv)->cclass = &nv31_mpeg_cclass;
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nv_engine(priv)->sclass = nv40_mpeg_sclass;
|
||||
nv_engine(priv)->tile_prog = nv31_mpeg_tile_prog;
|
||||
nv_subdev(mpeg)->unit = 0x00000002;
|
||||
nv_subdev(mpeg)->intr = nv40_mpeg_intr;
|
||||
nv_engine(mpeg)->cclass = &nv31_mpeg_cclass;
|
||||
nv_engine(mpeg)->sclass = nv40_mpeg_sclass;
|
||||
nv_engine(mpeg)->tile_prog = nv31_mpeg_tile_prog;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -27,10 +27,6 @@
|
|||
#include <core/handle.h>
|
||||
#include <engine/fifo.h>
|
||||
|
||||
struct nv44_mpeg_priv {
|
||||
struct nvkm_mpeg base;
|
||||
};
|
||||
|
||||
struct nv44_mpeg_chan {
|
||||
struct nvkm_mpeg_chan base;
|
||||
};
|
||||
|
|
@ -62,14 +58,14 @@ static int
|
|||
nv44_mpeg_context_fini(struct nvkm_object *object, bool suspend)
|
||||
{
|
||||
|
||||
struct nv44_mpeg_priv *priv = (void *)object->engine;
|
||||
struct nvkm_mpeg *mpeg = (void *)object->engine;
|
||||
struct nv44_mpeg_chan *chan = (void *)object;
|
||||
u32 inst = 0x80000000 | nv_gpuobj(chan)->addr >> 4;
|
||||
|
||||
nv_mask(priv, 0x00b32c, 0x00000001, 0x00000000);
|
||||
if (nv_rd32(priv, 0x00b318) == inst)
|
||||
nv_mask(priv, 0x00b318, 0x80000000, 0x00000000);
|
||||
nv_mask(priv, 0x00b32c, 0x00000001, 0x00000001);
|
||||
nv_mask(mpeg, 0x00b32c, 0x00000001, 0x00000000);
|
||||
if (nv_rd32(mpeg, 0x00b318) == inst)
|
||||
nv_mask(mpeg, 0x00b318, 0x80000000, 0x00000000);
|
||||
nv_mask(mpeg, 0x00b32c, 0x00000001, 0x00000001);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -97,12 +93,12 @@ nv44_mpeg_intr(struct nvkm_subdev *subdev)
|
|||
struct nvkm_engine *engine = nv_engine(subdev);
|
||||
struct nvkm_object *engctx;
|
||||
struct nvkm_handle *handle;
|
||||
struct nv44_mpeg_priv *priv = (void *)subdev;
|
||||
u32 inst = nv_rd32(priv, 0x00b318) & 0x000fffff;
|
||||
u32 stat = nv_rd32(priv, 0x00b100);
|
||||
u32 type = nv_rd32(priv, 0x00b230);
|
||||
u32 mthd = nv_rd32(priv, 0x00b234);
|
||||
u32 data = nv_rd32(priv, 0x00b238);
|
||||
struct nvkm_mpeg *mpeg = (void *)subdev;
|
||||
u32 inst = nv_rd32(mpeg, 0x00b318) & 0x000fffff;
|
||||
u32 stat = nv_rd32(mpeg, 0x00b100);
|
||||
u32 type = nv_rd32(mpeg, 0x00b230);
|
||||
u32 mthd = nv_rd32(mpeg, 0x00b234);
|
||||
u32 data = nv_rd32(mpeg, 0x00b238);
|
||||
u32 show = stat;
|
||||
int chid;
|
||||
|
||||
|
|
@ -112,7 +108,7 @@ nv44_mpeg_intr(struct nvkm_subdev *subdev)
|
|||
if (stat & 0x01000000) {
|
||||
/* happens on initial binding of the object */
|
||||
if (type == 0x00000020 && mthd == 0x0000) {
|
||||
nv_mask(priv, 0x00b308, 0x00000000, 0x00000000);
|
||||
nv_mask(mpeg, 0x00b308, 0x00000000, 0x00000000);
|
||||
show &= ~0x01000000;
|
||||
}
|
||||
|
||||
|
|
@ -124,11 +120,11 @@ nv44_mpeg_intr(struct nvkm_subdev *subdev)
|
|||
}
|
||||
}
|
||||
|
||||
nv_wr32(priv, 0x00b100, stat);
|
||||
nv_wr32(priv, 0x00b230, 0x00000001);
|
||||
nv_wr32(mpeg, 0x00b100, stat);
|
||||
nv_wr32(mpeg, 0x00b230, 0x00000001);
|
||||
|
||||
if (show) {
|
||||
nv_error(priv,
|
||||
nv_error(mpeg,
|
||||
"ch %d [0x%08x %s] 0x%08x 0x%08x 0x%08x 0x%08x\n",
|
||||
chid, inst << 4, nvkm_client_name(engctx), stat,
|
||||
type, mthd, data);
|
||||
|
|
@ -140,15 +136,15 @@ nv44_mpeg_intr(struct nvkm_subdev *subdev)
|
|||
static void
|
||||
nv44_mpeg_me_intr(struct nvkm_subdev *subdev)
|
||||
{
|
||||
struct nv44_mpeg_priv *priv = (void *)subdev;
|
||||
struct nvkm_mpeg *mpeg = (void *)subdev;
|
||||
u32 stat;
|
||||
|
||||
if ((stat = nv_rd32(priv, 0x00b100)))
|
||||
if ((stat = nv_rd32(mpeg, 0x00b100)))
|
||||
nv44_mpeg_intr(subdev);
|
||||
|
||||
if ((stat = nv_rd32(priv, 0x00b800))) {
|
||||
nv_error(priv, "PMSRCH 0x%08x\n", stat);
|
||||
nv_wr32(priv, 0x00b800, stat);
|
||||
if ((stat = nv_rd32(mpeg, 0x00b800))) {
|
||||
nv_error(mpeg, "PMSRCH 0x%08x\n", stat);
|
||||
nv_wr32(mpeg, 0x00b800, stat);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -157,19 +153,19 @@ nv44_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
|||
struct nvkm_oclass *oclass, void *data, u32 size,
|
||||
struct nvkm_object **pobject)
|
||||
{
|
||||
struct nv44_mpeg_priv *priv;
|
||||
struct nvkm_mpeg *mpeg;
|
||||
int ret;
|
||||
|
||||
ret = nvkm_mpeg_create(parent, engine, oclass, &priv);
|
||||
*pobject = nv_object(priv);
|
||||
ret = nvkm_mpeg_create(parent, engine, oclass, &mpeg);
|
||||
*pobject = nv_object(mpeg);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
nv_subdev(priv)->unit = 0x00000002;
|
||||
nv_subdev(priv)->intr = nv44_mpeg_me_intr;
|
||||
nv_engine(priv)->cclass = &nv44_mpeg_cclass;
|
||||
nv_engine(priv)->sclass = nv40_mpeg_sclass;
|
||||
nv_engine(priv)->tile_prog = nv31_mpeg_tile_prog;
|
||||
nv_subdev(mpeg)->unit = 0x00000002;
|
||||
nv_subdev(mpeg)->intr = nv44_mpeg_me_intr;
|
||||
nv_engine(mpeg)->cclass = &nv44_mpeg_cclass;
|
||||
nv_engine(mpeg)->sclass = nv40_mpeg_sclass;
|
||||
nv_engine(mpeg)->tile_prog = nv31_mpeg_tile_prog;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -26,10 +26,6 @@
|
|||
#include <subdev/bar.h>
|
||||
#include <subdev/timer.h>
|
||||
|
||||
struct nv50_mpeg_priv {
|
||||
struct nvkm_mpeg base;
|
||||
};
|
||||
|
||||
struct nv50_mpeg_chan {
|
||||
struct nvkm_mpeg_chan base;
|
||||
};
|
||||
|
|
@ -122,42 +118,42 @@ nv50_mpeg_cclass = {
|
|||
void
|
||||
nv50_mpeg_intr(struct nvkm_subdev *subdev)
|
||||
{
|
||||
struct nv50_mpeg_priv *priv = (void *)subdev;
|
||||
u32 stat = nv_rd32(priv, 0x00b100);
|
||||
u32 type = nv_rd32(priv, 0x00b230);
|
||||
u32 mthd = nv_rd32(priv, 0x00b234);
|
||||
u32 data = nv_rd32(priv, 0x00b238);
|
||||
struct nvkm_mpeg *mpeg = (void *)subdev;
|
||||
u32 stat = nv_rd32(mpeg, 0x00b100);
|
||||
u32 type = nv_rd32(mpeg, 0x00b230);
|
||||
u32 mthd = nv_rd32(mpeg, 0x00b234);
|
||||
u32 data = nv_rd32(mpeg, 0x00b238);
|
||||
u32 show = stat;
|
||||
|
||||
if (stat & 0x01000000) {
|
||||
/* happens on initial binding of the object */
|
||||
if (type == 0x00000020 && mthd == 0x0000) {
|
||||
nv_wr32(priv, 0x00b308, 0x00000100);
|
||||
nv_wr32(mpeg, 0x00b308, 0x00000100);
|
||||
show &= ~0x01000000;
|
||||
}
|
||||
}
|
||||
|
||||
if (show) {
|
||||
nv_info(priv, "0x%08x 0x%08x 0x%08x 0x%08x\n",
|
||||
nv_info(mpeg, "0x%08x 0x%08x 0x%08x 0x%08x\n",
|
||||
stat, type, mthd, data);
|
||||
}
|
||||
|
||||
nv_wr32(priv, 0x00b100, stat);
|
||||
nv_wr32(priv, 0x00b230, 0x00000001);
|
||||
nv_wr32(mpeg, 0x00b100, stat);
|
||||
nv_wr32(mpeg, 0x00b230, 0x00000001);
|
||||
}
|
||||
|
||||
static void
|
||||
nv50_vpe_intr(struct nvkm_subdev *subdev)
|
||||
{
|
||||
struct nv50_mpeg_priv *priv = (void *)subdev;
|
||||
struct nvkm_mpeg *mpeg = (void *)subdev;
|
||||
|
||||
if (nv_rd32(priv, 0x00b100))
|
||||
if (nv_rd32(mpeg, 0x00b100))
|
||||
nv50_mpeg_intr(subdev);
|
||||
|
||||
if (nv_rd32(priv, 0x00b800)) {
|
||||
u32 stat = nv_rd32(priv, 0x00b800);
|
||||
nv_info(priv, "PMSRCH: 0x%08x\n", stat);
|
||||
nv_wr32(priv, 0xb800, stat);
|
||||
if (nv_rd32(mpeg, 0x00b800)) {
|
||||
u32 stat = nv_rd32(mpeg, 0x00b800);
|
||||
nv_info(mpeg, "PMSRCH: 0x%08x\n", stat);
|
||||
nv_wr32(mpeg, 0xb800, stat);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -166,47 +162,47 @@ nv50_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
|||
struct nvkm_oclass *oclass, void *data, u32 size,
|
||||
struct nvkm_object **pobject)
|
||||
{
|
||||
struct nv50_mpeg_priv *priv;
|
||||
struct nvkm_mpeg *mpeg;
|
||||
int ret;
|
||||
|
||||
ret = nvkm_mpeg_create(parent, engine, oclass, &priv);
|
||||
*pobject = nv_object(priv);
|
||||
ret = nvkm_mpeg_create(parent, engine, oclass, &mpeg);
|
||||
*pobject = nv_object(mpeg);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
nv_subdev(priv)->unit = 0x00400002;
|
||||
nv_subdev(priv)->intr = nv50_vpe_intr;
|
||||
nv_engine(priv)->cclass = &nv50_mpeg_cclass;
|
||||
nv_engine(priv)->sclass = nv50_mpeg_sclass;
|
||||
nv_subdev(mpeg)->unit = 0x00400002;
|
||||
nv_subdev(mpeg)->intr = nv50_vpe_intr;
|
||||
nv_engine(mpeg)->cclass = &nv50_mpeg_cclass;
|
||||
nv_engine(mpeg)->sclass = nv50_mpeg_sclass;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
nv50_mpeg_init(struct nvkm_object *object)
|
||||
{
|
||||
struct nv50_mpeg_priv *priv = (void *)object;
|
||||
struct nvkm_mpeg *mpeg = (void *)object;
|
||||
int ret;
|
||||
|
||||
ret = nvkm_mpeg_init(&priv->base);
|
||||
ret = nvkm_mpeg_init(mpeg);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
nv_wr32(priv, 0x00b32c, 0x00000000);
|
||||
nv_wr32(priv, 0x00b314, 0x00000100);
|
||||
nv_wr32(priv, 0x00b0e0, 0x0000001a);
|
||||
nv_wr32(mpeg, 0x00b32c, 0x00000000);
|
||||
nv_wr32(mpeg, 0x00b314, 0x00000100);
|
||||
nv_wr32(mpeg, 0x00b0e0, 0x0000001a);
|
||||
|
||||
nv_wr32(priv, 0x00b220, 0x00000044);
|
||||
nv_wr32(priv, 0x00b300, 0x00801ec1);
|
||||
nv_wr32(priv, 0x00b390, 0x00000000);
|
||||
nv_wr32(priv, 0x00b394, 0x00000000);
|
||||
nv_wr32(priv, 0x00b398, 0x00000000);
|
||||
nv_mask(priv, 0x00b32c, 0x00000001, 0x00000001);
|
||||
nv_wr32(mpeg, 0x00b220, 0x00000044);
|
||||
nv_wr32(mpeg, 0x00b300, 0x00801ec1);
|
||||
nv_wr32(mpeg, 0x00b390, 0x00000000);
|
||||
nv_wr32(mpeg, 0x00b394, 0x00000000);
|
||||
nv_wr32(mpeg, 0x00b398, 0x00000000);
|
||||
nv_mask(mpeg, 0x00b32c, 0x00000001, 0x00000001);
|
||||
|
||||
nv_wr32(priv, 0x00b100, 0xffffffff);
|
||||
nv_wr32(priv, 0x00b140, 0xffffffff);
|
||||
nv_wr32(mpeg, 0x00b100, 0xffffffff);
|
||||
nv_wr32(mpeg, 0x00b140, 0xffffffff);
|
||||
|
||||
if (!nv_wait(priv, 0x00b200, 0x00000001, 0x00000000)) {
|
||||
nv_error(priv, "timeout 0x%08x\n", nv_rd32(priv, 0x00b200));
|
||||
if (!nv_wait(mpeg, 0x00b200, 0x00000001, 0x00000000)) {
|
||||
nv_error(mpeg, "timeout 0x%08x\n", nv_rd32(mpeg, 0x00b200));
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue