drm/i915: Read out memory type
We'll need to know the memory type in the system for some bandwidth limitations and whatnot. Let's read that out on gen9+. v2: Rebase v3: Fix the copy paste fail in the BXT bit definitions (Jani) Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190306203551.24592-13-ville.syrjala@linux.intel.com
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drivers/gpu/drm/i915
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@ -1068,6 +1068,26 @@ static void intel_sanitize_options(struct drm_i915_private *dev_priv)
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intel_gvt_sanitize_options(dev_priv);
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}
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#define DRAM_TYPE_STR(type) [INTEL_DRAM_ ## type] = #type
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static const char *intel_dram_type_str(enum intel_dram_type type)
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{
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static const char * const str[] = {
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DRAM_TYPE_STR(UNKNOWN),
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DRAM_TYPE_STR(DDR3),
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DRAM_TYPE_STR(DDR4),
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DRAM_TYPE_STR(LPDDR3),
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DRAM_TYPE_STR(LPDDR4),
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};
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if (type >= ARRAY_SIZE(str))
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type = INTEL_DRAM_UNKNOWN;
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return str[type];
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}
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#undef DRAM_TYPE_STR
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static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
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{
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return dimm->ranks * 64 / (dimm->width ?: 1);
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@ -1254,6 +1274,28 @@ skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
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return 0;
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}
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static enum intel_dram_type
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skl_get_dram_type(struct drm_i915_private *dev_priv)
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{
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u32 val;
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val = I915_READ(SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
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switch (val & SKL_DRAM_DDR_TYPE_MASK) {
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case SKL_DRAM_DDR_TYPE_DDR3:
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return INTEL_DRAM_DDR3;
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case SKL_DRAM_DDR_TYPE_DDR4:
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return INTEL_DRAM_DDR4;
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case SKL_DRAM_DDR_TYPE_LPDDR3:
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return INTEL_DRAM_LPDDR3;
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case SKL_DRAM_DDR_TYPE_LPDDR4:
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return INTEL_DRAM_LPDDR4;
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default:
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MISSING_CASE(val);
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return INTEL_DRAM_UNKNOWN;
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}
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}
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static int
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skl_get_dram_info(struct drm_i915_private *dev_priv)
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{
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@ -1261,6 +1303,9 @@ skl_get_dram_info(struct drm_i915_private *dev_priv)
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u32 mem_freq_khz, val;
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int ret;
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dram_info->type = skl_get_dram_type(dev_priv);
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DRM_DEBUG_KMS("DRAM type: %s\n", intel_dram_type_str(dram_info->type));
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ret = skl_dram_get_channels_info(dev_priv);
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if (ret)
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return ret;
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@ -1327,6 +1372,26 @@ static int bxt_get_dimm_ranks(u32 val)
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}
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}
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static enum intel_dram_type bxt_get_dimm_type(u32 val)
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{
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if (!bxt_get_dimm_size(val))
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return INTEL_DRAM_UNKNOWN;
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switch (val & BXT_DRAM_TYPE_MASK) {
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case BXT_DRAM_TYPE_DDR3:
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return INTEL_DRAM_DDR3;
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case BXT_DRAM_TYPE_LPDDR3:
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return INTEL_DRAM_LPDDR3;
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case BXT_DRAM_TYPE_DDR4:
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return INTEL_DRAM_DDR4;
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case BXT_DRAM_TYPE_LPDDR4:
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return INTEL_DRAM_LPDDR4;
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default:
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MISSING_CASE(val);
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return INTEL_DRAM_UNKNOWN;
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}
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}
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static void bxt_get_dimm_info(struct dram_dimm_info *dimm,
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u32 val)
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{
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@ -1369,6 +1434,7 @@ bxt_get_dram_info(struct drm_i915_private *dev_priv)
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*/
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for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) {
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struct dram_dimm_info dimm;
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enum intel_dram_type type;
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val = I915_READ(BXT_D_CR_DRP0_DUNIT(i));
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if (val == 0xFFFFFFFF)
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@ -1377,10 +1443,16 @@ bxt_get_dram_info(struct drm_i915_private *dev_priv)
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dram_info->num_channels++;
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bxt_get_dimm_info(&dimm, val);
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type = bxt_get_dimm_type(val);
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DRM_DEBUG_KMS("CH%u DIMM size: %u GB, width: X%u, ranks: %u\n",
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WARN_ON(type != INTEL_DRAM_UNKNOWN &&
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dram_info->type != INTEL_DRAM_UNKNOWN &&
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dram_info->type != type);
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DRM_DEBUG_KMS("CH%u DIMM size: %u GB, width: X%u, ranks: %u, type: %s\n",
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i - BXT_D_CR_DRP0_DUNIT_START,
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dimm.size, dimm.width, dimm.ranks);
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dimm.size, dimm.width, dimm.ranks,
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intel_dram_type_str(type));
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/*
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* If any of the channel is single rank channel,
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@ -1391,10 +1463,14 @@ bxt_get_dram_info(struct drm_i915_private *dev_priv)
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dram_info->ranks = dimm.ranks;
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else if (dimm.ranks == 1)
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dram_info->ranks = 1;
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if (type != INTEL_DRAM_UNKNOWN)
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dram_info->type = type;
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}
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if (dram_info->ranks == 0) {
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DRM_INFO("couldn't get memory rank information\n");
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if (dram_info->type == INTEL_DRAM_UNKNOWN ||
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dram_info->ranks == 0) {
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DRM_INFO("couldn't get memory information\n");
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return -EINVAL;
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}
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@ -1829,6 +1829,13 @@ struct drm_i915_private {
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u8 ranks;
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u32 bandwidth_kbps;
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bool symmetric_memory;
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enum intel_dram_type {
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INTEL_DRAM_UNKNOWN,
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INTEL_DRAM_DDR3,
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INTEL_DRAM_DDR4,
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INTEL_DRAM_LPDDR3,
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INTEL_DRAM_LPDDR4
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} type;
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} dram_info;
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struct i915_runtime_pm runtime_pm;
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@ -9861,11 +9861,24 @@ enum skl_power_gate {
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#define BXT_DRAM_SIZE_8GBIT (0x2 << 6)
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#define BXT_DRAM_SIZE_12GBIT (0x3 << 6)
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#define BXT_DRAM_SIZE_16GBIT (0x4 << 6)
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#define BXT_DRAM_TYPE_MASK (0x7 << 22)
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#define BXT_DRAM_TYPE_SHIFT 22
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#define BXT_DRAM_TYPE_DDR3 (0x0 << 22)
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#define BXT_DRAM_TYPE_LPDDR3 (0x1 << 22)
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#define BXT_DRAM_TYPE_LPDDR4 (0x2 << 22)
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#define BXT_DRAM_TYPE_DDR4 (0x4 << 22)
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#define SKL_MEMORY_FREQ_MULTIPLIER_HZ 266666666
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#define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04)
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#define SKL_REQ_DATA_MASK (0xF << 0)
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#define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)
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#define SKL_DRAM_DDR_TYPE_MASK (0x3 << 0)
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#define SKL_DRAM_DDR_TYPE_DDR4 (0 << 0)
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#define SKL_DRAM_DDR_TYPE_DDR3 (1 << 0)
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#define SKL_DRAM_DDR_TYPE_LPDDR3 (2 << 0)
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#define SKL_DRAM_DDR_TYPE_LPDDR4 (3 << 0)
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#define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
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#define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
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#define SKL_DRAM_S_SHIFT 16
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