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drm/amd/pm: Add atom_smc_dpm_info_v4_10 for aldebaran 

Add atom_smc_dpm_info_v4_10 that defines board parameters for aldebaran

Signed-off-by: Lijo Lazar <Lijo.Lazar@amd.com>
Reviewed-by: Kenneth Feng <Kenneth.Feng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Lijo Lazar 2020-11-28 16:38:56 +08:00 committed by Alex Deucher
parent be566196be
commit b1138d5ec0
2 changed files with 75 additions and 0 deletions
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53
drivers/gpu/drm/amd/include/atomfirmware.h
View File

@ -2335,6 +2335,59 @@ struct atom_smc_dpm_info_v4_9
};
struct atom_smc_dpm_info_v4_10
{
struct atom_common_table_header table_header;
// SECTION: BOARD PARAMETERS
// Telemetry Settings
uint16_t GfxMaxCurrent; // in Amps
uint8_t GfxOffset; // in Amps
uint8_t Padding_TelemetryGfx;
uint16_t SocMaxCurrent; // in Amps
uint8_t SocOffset; // in Amps
uint8_t Padding_TelemetrySoc;
uint16_t MemMaxCurrent; // in Amps
uint8_t MemOffset; // in Amps
uint8_t Padding_TelemetryMem;
uint16_t BoardMaxCurrent; // in Amps
uint8_t BoardOffset; // in Amps
uint8_t Padding_TelemetryBoardInput;
// Platform input telemetry voltage coefficient
uint32_t BoardVoltageCoeffA; // decode by /1000
uint32_t BoardVoltageCoeffB; // decode by /1000
// GPIO Settings
uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
// UCLK Spread Spectrum
uint8_t UclkSpreadEnabled; // on or off
uint8_t UclkSpreadPercent; // Q4.4
uint16_t UclkSpreadFreq; // kHz
// FCLK Spread Spectrum
uint8_t FclkSpreadEnabled; // on or off
uint8_t FclkSpreadPercent; // Q4.4
uint16_t FclkSpreadFreq; // kHz
// I2C Controller Structure
struct smudpm_i2c_controller_config_v3 I2cControllers[8];
// GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence
uint8_t GpioI2cScl; // Serial Clock
uint8_t GpioI2cSda; // Serial Data
uint16_t spare5;
uint32_t reserved[16];
};
/*
***************************************************************************
Data Table asic_profiling_info structure

22
drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
View File

@ -377,6 +377,28 @@ static int aldebaran_store_powerplay_table(struct smu_context *smu)
static int aldebaran_append_powerplay_table(struct smu_context *smu)
{
struct smu_table_context *table_context = &smu->smu_table;
PPTable_t *smc_pptable = table_context->driver_pptable;
struct atom_smc_dpm_info_v4_10 *smc_dpm_table;
int index, ret;
index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
smc_dpm_info);
ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
(uint8_t **)&smc_dpm_table);
if (ret)
return ret;
dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
smc_dpm_table->table_header.format_revision,
smc_dpm_table->table_header.content_revision);
if ((smc_dpm_table->table_header.format_revision == 4) &&
(smc_dpm_table->table_header.content_revision == 10))
memcpy(&smc_pptable->GfxMaxCurrent,
&smc_dpm_table->GfxMaxCurrent,
sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_10, GfxMaxCurrent));
return 0;
}