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drm/i915: Simplify intel_get_crtc_ycbcr_config() 

Make intel_get_crtc_ycbcr_config() simpler and rename it
to bdw_get_pipemisc_output_format() to better reflect what
it does.

Also toss in some comments to document that the 4:2:0 PIPECONF
bits are glk+ only. They are mbz on earlier platforms so reading
them unconditionally is safe however.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190718145053.25808-9-ville.syrjala@linux.intel.com
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
This commit is contained in:
Ville Syrjälä 2019-07-18 17:50:49 +03:00
parent 60a02311cc
commit b10d1173ee
2 changed files with 31 additions and 38 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

65
drivers/gpu/drm/i915/display/intel_display.c
View File

@ -8727,47 +8727,24 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc,
pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
}
static void intel_get_crtc_ycbcr_config(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
static enum intel_output_format
bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum intel_output_format output = INTEL_OUTPUT_FORMAT_RGB;
u32 tmp;
pipe_config->lspcon_downsampling = false;
tmp = I915_READ(PIPEMISC(crtc->pipe));
if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
if (tmp & PIPEMISC_YUV420_ENABLE) {
/* We support 4:2:0 in full blend mode only */
WARN_ON((tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0);
if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
bool ycbcr420_enabled = tmp & PIPEMISC_YUV420_ENABLE;
bool blend = tmp & PIPEMISC_YUV420_MODE_FULL_BLEND;
if (ycbcr420_enabled) {
/* We support 4:2:0 in full blend mode only */
if (!blend)
output = INTEL_OUTPUT_FORMAT_INVALID;
else if (!(IS_GEMINILAKE(dev_priv) ||
INTEL_GEN(dev_priv) >= 10))
output = INTEL_OUTPUT_FORMAT_INVALID;
else
output = INTEL_OUTPUT_FORMAT_YCBCR420;
} else {
/*
* Currently there is no interface defined to
* check user preference between RGB/YCBCR444
* or YCBCR420. So the only possible case for
* YCBCR444 usage is driving YCBCR420 output
* with LSPCON, when pipe is configured for
* YCBCR444 output and LSPCON takes care of
* downsampling it.
*/
pipe_config->lspcon_downsampling = true;
output = INTEL_OUTPUT_FORMAT_YCBCR444;
}
}
return INTEL_OUTPUT_FORMAT_YCBCR420;
} else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
return INTEL_OUTPUT_FORMAT_YCBCR444;
} else {
return INTEL_OUTPUT_FORMAT_RGB;
}
pipe_config->output_format = output;
}
static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
@ -10462,7 +10439,23 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
}
intel_get_pipe_src_size(crtc, pipe_config);
intel_get_crtc_ycbcr_config(crtc, pipe_config);
if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) {
pipe_config->output_format =
bdw_get_pipemisc_output_format(crtc);
/*
* Currently there is no interface defined to
* check user preference between RGB/YCBCR444
* or YCBCR420. So the only possible case for
* YCBCR444 usage is driving YCBCR420 output
* with LSPCON, when pipe is configured for
* YCBCR444 output and LSPCON takes care of
* downsampling it.
*/
pipe_config->lspcon_downsampling =
pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444;
}
pipe_config->gamma_mode = I915_READ(GAMMA_MODE(crtc->pipe));

4
drivers/gpu/drm/i915/i915_reg.h
View File

@ -5775,8 +5775,8 @@ enum {
#define _PIPE_MISC_A 0x70030
#define _PIPE_MISC_B 0x71030
#define PIPEMISC_YUV420_ENABLE (1 << 27)
#define PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26)
#define PIPEMISC_YUV420_ENABLE (1 << 27) /* glk+ */
#define PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26) /* glk+ */
#define PIPEMISC_HDR_MODE_PRECISION (1 << 23) /* icl+ */
#define PIPEMISC_OUTPUT_COLORSPACE_YUV (1 << 11)
#define PIPEMISC_DITHER_BPC_MASK (7 << 5)