ARM: 5978/1: plat-nomadik: use one-shot clock events
This is a complete rewrite of the MTU driver, using one-shot for events and a free-running timer for stamping. It allows CONFIG_NO_HZ and CONFIG_HIGH_RES_TIMERS to work on Nomadik and Ux500. Signed-off-by: Alessandro Rubini <rubini@unipv.it> Acked-by: Linus Walleij <linus.walleij@stericsson.com> Acked-by: Andrea Gallo <andrea.gallo@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Alessandro Rubini
Russell King
parent
94bdc0e2d7
commit
b102c01fae
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@ -2,7 +2,7 @@
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* linux/arch/arm/mach-nomadik/timer.c
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*
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* Copyright (C) 2008 STMicroelectronics
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* Copyright (C) 2009 Alessandro Rubini, somewhat based on at91sam926x
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* Copyright (C) 2010 Alessandro Rubini
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2, as
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@ -18,123 +18,124 @@
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#include <plat/mtu.h>
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static u32 nmdk_count; /* accumulated count */
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static u32 nmdk_cycle; /* write-once */
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void __iomem *mtu_base; /* ssigned by machine code */
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/* setup by the platform code */
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void __iomem *mtu_base;
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/*
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* clocksource: the MTU device is a decrementing counters, so we negate
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* the value being read.
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*/
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/* clocksource: MTU decrements, so we negate the value being read. */
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static cycle_t nmdk_read_timer(struct clocksource *cs)
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{
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u32 count = readl(mtu_base + MTU_VAL(0));
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return nmdk_count + nmdk_cycle - count;
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return -readl(mtu_base + MTU_VAL(0));
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}
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static struct clocksource nmdk_clksrc = {
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.name = "mtu_0",
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.rating = 120,
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.rating = 200,
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.read = nmdk_read_timer,
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.mask = CLOCKSOURCE_MASK(32),
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.shift = 20,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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/*
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* Clockevent device: currently only periodic mode is supported
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*/
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/* Clockevent device: use one-shot mode */
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static void nmdk_clkevt_mode(enum clock_event_mode mode,
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struct clock_event_device *dev)
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{
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u32 cr;
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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/* count current value? */
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writel(readl(mtu_base + MTU_IMSC) | 1, mtu_base + MTU_IMSC);
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pr_err("%s: periodic mode not supported\n", __func__);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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BUG(); /* Not supported, yet */
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/* FALLTHROUGH */
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/* Load highest value, enable device, enable interrupts */
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cr = readl(mtu_base + MTU_CR(1));
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writel(0, mtu_base + MTU_LR(1));
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writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(1));
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writel(0x2, mtu_base + MTU_IMSC);
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break;
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_UNUSED:
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writel(readl(mtu_base + MTU_IMSC) & ~1, mtu_base + MTU_IMSC);
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/* disable irq */
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writel(0, mtu_base + MTU_IMSC);
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break;
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case CLOCK_EVT_MODE_RESUME:
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break;
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}
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}
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static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
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{
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/* writing the value has immediate effect */
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writel(evt, mtu_base + MTU_LR(1));
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return 0;
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}
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static struct clock_event_device nmdk_clkevt = {
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.name = "mtu_0",
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.features = CLOCK_EVT_FEAT_PERIODIC,
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.name = "mtu_1",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.shift = 32,
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.rating = 100,
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.rating = 200,
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.set_mode = nmdk_clkevt_mode,
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.set_next_event = nmdk_clkevt_next,
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};
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/*
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* IRQ Handler for the timer 0 of the MTU block. The irq is not shared
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* as we are the only users of mtu0 by now.
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* IRQ Handler for timer 1 of the MTU block.
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*/
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static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
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{
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/* ack: "interrupt clear register" */
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writel(1 << 0, mtu_base + MTU_ICR);
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/* we can't count lost ticks, unfortunately */
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nmdk_count += nmdk_cycle;
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nmdk_clkevt.event_handler(&nmdk_clkevt);
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struct clock_event_device *evdev = dev_id;
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writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */
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evdev->event_handler(evdev);
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return IRQ_HANDLED;
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}
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/*
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* Set up timer interrupt, and return the current time in seconds.
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*/
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static struct irqaction nmdk_timer_irq = {
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.name = "Nomadik Timer Tick",
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.flags = IRQF_DISABLED | IRQF_TIMER,
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.handler = nmdk_timer_interrupt,
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.dev_id = &nmdk_clkevt,
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};
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static void nmdk_timer_reset(void)
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{
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u32 cr;
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writel(0, mtu_base + MTU_CR(0)); /* off */
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/* configure load and background-load, and fire it up */
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writel(nmdk_cycle, mtu_base + MTU_LR(0));
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writel(nmdk_cycle, mtu_base + MTU_BGLR(0));
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cr = MTU_CRn_PERIODIC | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS;
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writel(cr, mtu_base + MTU_CR(0));
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writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0));
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}
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void __init nmdk_timer_init(void)
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{
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unsigned long rate;
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int bits;
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u32 cr = MTU_CRn_32BITS;;
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rate = CLOCK_TICK_RATE; /* 2.4MHz */
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nmdk_cycle = (rate + HZ/2) / HZ;
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/*
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* Tick rate is 2.4MHz for Nomadik and 110MHz for ux500:
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* use a divide-by-16 counter if it's more than 16MHz
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*/
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rate = CLOCK_TICK_RATE;
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if (rate > 16 << 20) {
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rate /= 16;
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cr |= MTU_CRn_PRESCALE_16;
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} else {
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cr |= MTU_CRn_PRESCALE_1;
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}
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/* Init the timer and register clocksource */
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nmdk_timer_reset();
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/* Timer 0 is the free running clocksource */
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writel(cr, mtu_base + MTU_CR(0));
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writel(0, mtu_base + MTU_LR(0));
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writel(0, mtu_base + MTU_BGLR(0));
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writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0));
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nmdk_clksrc.mult = clocksource_hz2mult(rate, nmdk_clksrc.shift);
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bits = 8*sizeof(nmdk_count);
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nmdk_clksrc.mask = CLOCKSOURCE_MASK(bits);
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if (clocksource_register(&nmdk_clksrc))
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printk(KERN_ERR "timer: failed to initialize clock "
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"source %s\n", nmdk_clksrc.name);
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pr_err("timer: failed to initialize clock source %s\n",
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nmdk_clksrc.name);
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/* Timer 1 is used for events, fix according to rate */
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writel(cr | MTU_CRn_ONESHOT, mtu_base + MTU_CR(1)); /* off, currently */
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nmdk_clkevt.mult = div_sc(rate, NSEC_PER_SEC, nmdk_clkevt.shift);
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nmdk_clkevt.max_delta_ns =
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clockevent_delta2ns(0xffffffff, &nmdk_clkevt);
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nmdk_clkevt.min_delta_ns =
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clockevent_delta2ns(0x00000002, &nmdk_clkevt);
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nmdk_clkevt.cpumask = cpumask_of(0);
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/* Register irq and clockevents */
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setup_irq(IRQ_MTU0, &nmdk_timer_irq);
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nmdk_clkevt.mult = div_sc(rate, NSEC_PER_SEC, nmdk_clkevt.shift);
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nmdk_clkevt.cpumask = cpumask_of(0);
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clockevents_register_device(&nmdk_clkevt);
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}
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