powerpc/85xx: Rework P1023RDS device tree
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Dropping "fsl,p1023-IP..." from compatibles for standard blocks * Removed incorrect power/pmc node, there are no etsec on P1023 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala
parent
ab827d97bd
commit
b0e2f248b4
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@ -0,0 +1,224 @@
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/*
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* P1023/P1017 Silicon/SoC Device Tree Source (post include)
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*
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* Copyright 2011 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
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||||
*
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||||
*
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||||
* ALTERNATIVELY, this software may be distributed under the terms of the
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||||
* GNU General Public License ("GPL") as published by the Free Software
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||||
* Foundation, either version 2 of that License or (at your option) any
|
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* later version.
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||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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&lbc {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "fsl,p1023-elbc", "fsl,elbc", "simple-bus";
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interrupts = <19 2 0 0>;
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};
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/* controller at 0xa000 */
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&pci0 {
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compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
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device_type = "pci";
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#size-cells = <2>;
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#address-cells = <3>;
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bus-range = <0x0 0xff>;
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clock-frequency = <33333333>;
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interrupts = <16 2 0 0>;
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pcie@0 {
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reg = <0 0 0 0 0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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interrupts = <16 2 0 0>;
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};
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};
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/* controller at 0x9000 */
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&pci1 {
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compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
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device_type = "pci";
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#size-cells = <2>;
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#address-cells = <3>;
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bus-range = <0 0xff>;
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clock-frequency = <33333333>;
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interrupts = <16 2 0 0>;
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pcie@0 {
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reg = <0 0 0 0 0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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interrupts = <16 2 0 0>;
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};
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};
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/* controller at 0xb000 */
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&pci2 {
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compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
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device_type = "pci";
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#size-cells = <2>;
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#address-cells = <3>;
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bus-range = <0x0 0xff>;
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clock-frequency = <33333333>;
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interrupts = <16 2 0 0>;
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pcie@0 {
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reg = <0 0 0 0 0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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interrupts = <16 2 0 0>;
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};
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "fsl,p1023-immr", "simple-bus";
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bus-frequency = <0>; // Filled out by uboot.
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ecm-law@0 {
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compatible = "fsl,ecm-law";
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reg = <0x0 0x1000>;
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fsl,num-laws = <12>;
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};
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ecm@1000 {
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compatible = "fsl,p1023-ecm", "fsl,ecm";
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reg = <0x1000 0x1000>;
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interrupts = <16 2 0 0>;
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};
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memory-controller@2000 {
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compatible = "fsl,p1023-memory-controller";
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reg = <0x2000 0x1000>;
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interrupts = <16 2 0 0>;
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};
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/include/ "pq3-i2c-0.dtsi"
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/include/ "pq3-i2c-1.dtsi"
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/include/ "pq3-duart-0.dtsi"
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/include/ "pq3-espi-0.dtsi"
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spi@7000 {
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fsl,espi-num-chipselects = <4>;
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};
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/include/ "pq3-gpio-0.dtsi"
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L2: l2-cache-controller@20000 {
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compatible = "fsl,p1023-l2-cache-controller";
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reg = <0x20000 0x1000>;
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cache-line-size = <32>; // 32 bytes
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cache-size = <0x40000>; // L2,256K
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interrupts = <16 2 0 0>;
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};
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/include/ "pq3-dma-0.dtsi"
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/include/ "pq3-usb2-dr-0.dtsi"
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crypto: crypto@300000 {
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compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x30000 0x10000>;
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ranges = <0 0x30000 0x10000>;
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interrupts = <58 2 0 0>;
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sec_jr0: jr@1000 {
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compatible = "fsl,sec-v4.2-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x1000 0x1000>;
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interrupts = <45 2 0 0>;
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};
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sec_jr1: jr@2000 {
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compatible = "fsl,sec-v4.2-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x2000 0x1000>;
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interrupts = <45 2 0 0>;
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};
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sec_jr2: jr@3000 {
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compatible = "fsl,sec-v4.2-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x3000 0x1000>;
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interrupts = <57 2 0 0>;
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};
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sec_jr3: jr@4000 {
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compatible = "fsl,sec-v4.2-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x4000 0x1000>;
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interrupts = <57 2 0 0>;
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};
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rtic@6000 {
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compatible = "fsl,sec-v4.2-rtic",
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"fsl,sec-v4.0-rtic";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x6000 0x100>;
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ranges = <0x0 0x6100 0xe00>;
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rtic_a: rtic-a@0 {
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compatible = "fsl,sec-v4.2-rtic-memory",
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"fsl,sec-v4.0-rtic-memory";
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reg = <0x00 0x20 0x100 0x80>;
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};
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rtic_b: rtic-b@20 {
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compatible = "fsl,sec-v4.2-rtic-memory",
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"fsl,sec-v4.0-rtic-memory";
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reg = <0x20 0x20 0x200 0x80>;
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};
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rtic_c: rtic-c@40 {
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compatible = "fsl,sec-v4.2-rtic-memory",
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"fsl,sec-v4.0-rtic-memory";
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reg = <0x40 0x20 0x300 0x80>;
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};
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rtic_d: rtic-d@60 {
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compatible = "fsl,sec-v4.2-rtic-memory",
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"fsl,sec-v4.0-rtic-memory";
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reg = <0x60 0x20 0x500 0x80>;
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};
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};
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};
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/include/ "pq3-mpic.dtsi"
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/include/ "pq3-mpic-timer-B.dtsi"
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global-utilities@e0000 {
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compatible = "fsl,p1023-guts";
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reg = <0xe0000 0x1000>;
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fsl,has-rstcr;
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};
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};
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@ -0,0 +1,76 @@
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/*
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* P1023/P1017 Silicon/SoC Device Tree Source (pre include)
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*
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* Copyright 2011 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
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* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/dts-v1/;
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/ {
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compatible = "fsl,P1023";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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aliases {
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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pci1 = &pci1;
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pci2 = &pci2;
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crypto = &crypto;
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sec_jr0 = &sec_jr0;
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sec_jr1 = &sec_jr1;
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sec_jr2 = &sec_jr2;
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sec_jr3 = &sec_jr3;
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rtic_a = &rtic_a;
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rtic_b = &rtic_b;
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rtic_c = &rtic_c;
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rtic_d = &rtic_d;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,P1023@0 {
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device_type = "cpu";
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reg = <0x0>;
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next-level-cache = <&L2>;
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};
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PowerPC,P1023@1 {
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device_type = "cpu";
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reg = <0x1>;
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next-level-cache = <&L2>;
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};
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};
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};
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@ -34,137 +34,30 @@
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/dts-v1/;
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/include/ "fsl/p1023si-pre.dtsi"
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/ {
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model = "fsl,P1023";
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compatible = "fsl,P1023RDS";
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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pci1 = &pci1;
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pci2 = &pci2;
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crypto = &crypto;
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sec_jr0 = &sec_jr0;
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sec_jr1 = &sec_jr1;
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sec_jr2 = &sec_jr2;
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sec_jr3 = &sec_jr3;
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rtic_a = &rtic_a;
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rtic_b = &rtic_b;
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rtic_c = &rtic_c;
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rtic_d = &rtic_d;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: PowerPC,P1023@0 {
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device_type = "cpu";
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reg = <0x0>;
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next-level-cache = <&L2>;
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};
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cpu1: PowerPC,P1023@1 {
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device_type = "cpu";
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reg = <0x1>;
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next-level-cache = <&L2>;
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};
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};
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interrupt-parent = <&mpic>;
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memory {
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device_type = "memory";
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};
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soc@ff600000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "fsl,p1023-immr", "simple-bus";
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soc: soc@ff600000 {
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ranges = <0x0 0x0 0xff600000 0x200000>;
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bus-frequency = <0>; // Filled out by uboot.
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ecm-law@0 {
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compatible = "fsl,ecm-law";
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reg = <0x0 0x1000>;
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fsl,num-laws = <12>;
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};
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ecm@1000 {
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compatible = "fsl,p1023-ecm", "fsl,ecm";
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reg = <0x1000 0x1000>;
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interrupts = <16 2>;
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interrupt-parent = <&mpic>;
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};
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memory-controller@2000 {
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compatible = "fsl,p1023-memory-controller";
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reg = <0x2000 0x1000>;
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||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
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};
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||||
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||||
i2c@3000 {
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#address-cells = <1>;
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||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
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||||
rtc@68 {
|
||||
compatible = "dallas,ds1374";
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reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
cell-index = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,p1023-espi", "fsl,mpc8536-espi";
|
||||
reg = <0x7000 0x1000>;
|
||||
interrupts = <59 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,espi-num-chipselects = <4>;
|
||||
|
||||
fsl_dataflash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -186,197 +79,14 @@
|
|||
};
|
||||
};
|
||||
|
||||
gpio: gpio-controller@f000 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "fsl,qoriq-gpio";
|
||||
reg = <0xf000 0x100>;
|
||||
interrupts = <47 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,p1023-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x40000>; // L2,256K
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
usb@22000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x22000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <28 0x2>;
|
||||
dr_mode = "host";
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
crypto: crypto@300000 {
|
||||
compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x30000 0x10000>;
|
||||
ranges = <0 0x30000 0x10000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <58 2>;
|
||||
|
||||
sec_jr0: jr@1000 {
|
||||
compatible = "fsl,sec-v4.2-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <45 2>;
|
||||
};
|
||||
|
||||
sec_jr1: jr@2000 {
|
||||
compatible = "fsl,sec-v4.2-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <45 2>;
|
||||
};
|
||||
|
||||
sec_jr2: jr@3000 {
|
||||
compatible = "fsl,sec-v4.2-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x3000 0x1000>;
|
||||
interrupts = <57 2>;
|
||||
};
|
||||
|
||||
sec_jr3: jr@4000 {
|
||||
compatible = "fsl,sec-v4.2-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x4000 0x1000>;
|
||||
interrupts = <57 2>;
|
||||
};
|
||||
|
||||
rtic@6000 {
|
||||
compatible = "fsl,sec-v4.2-rtic",
|
||||
"fsl,sec-v4.0-rtic";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x6000 0x100>;
|
||||
ranges = <0x0 0x6100 0xe00>;
|
||||
|
||||
rtic_a: rtic-a@0 {
|
||||
compatible = "fsl,sec-v4.2-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x00 0x20 0x100 0x80>;
|
||||
};
|
||||
|
||||
rtic_b: rtic-b@20 {
|
||||
compatible = "fsl,sec-v4.2-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x20 0x20 0x200 0x80>;
|
||||
};
|
||||
|
||||
rtic_c: rtic-c@40 {
|
||||
compatible = "fsl,sec-v4.2-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x40 0x20 0x300 0x80>;
|
||||
};
|
||||
|
||||
rtic_d: rtic-d@60 {
|
||||
compatible = "fsl,sec-v4.2-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x60 0x20 0x500 0x80>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
power@e0070{
|
||||
compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc",
|
||||
"fsl,p1022-pmc";
|
||||
reg = <0xe0070 0x20>;
|
||||
etsec1_clk: soc-clk@B0{
|
||||
fsl,pmcdr-mask = <0x00000080>;
|
||||
};
|
||||
etsec2_clk: soc-clk@B1{
|
||||
fsl,pmcdr-mask = <0x00000040>;
|
||||
};
|
||||
etsec3_clk: soc-clk@B2{
|
||||
fsl,pmcdr-mask = <0x00000020>;
|
||||
};
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
msi@41600 {
|
||||
compatible = "fsl,p1023-msi", "fsl,mpic-msi";
|
||||
reg = <0x41600 0x80>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe0 0
|
||||
0xe1 0
|
||||
0xe2 0
|
||||
0xe3 0
|
||||
0xe4 0
|
||||
0xe5 0
|
||||
0xe6 0
|
||||
0xe7 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 { //global utilities block
|
||||
compatible = "fsl,p1023-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
|
||||
localbus@ff605000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,p1023-elbc", "fsl,elbc", "simple-bus";
|
||||
lbc: localbus@ff605000 {
|
||||
reg = <0 0xff605000 0 0x1000>;
|
||||
interrupts = <19 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
/* NOR Flash, BCSR */
|
||||
ranges = <0x0 0x0 0x0 0xee000000 0x02000000
|
||||
|
|
@ -428,34 +138,18 @@
|
|||
};
|
||||
|
||||
pci0: pcie@ff60a000 {
|
||||
compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
|
||||
cell-index = <1>;
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xff60a000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
|
||||
0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
pcie@0 {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
/* IRQ[0:3] are pulled up on board, set to active-low */
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 0 1
|
||||
0000 0 0 2 &mpic 1 1
|
||||
0000 0 0 3 &mpic 2 1
|
||||
0000 0 0 4 &mpic 3 1
|
||||
0000 0 0 1 &mpic 0 1 0 0
|
||||
0000 0 0 2 &mpic 1 1 0 0
|
||||
0000 0 0 3 &mpic 2 1 0 0
|
||||
0000 0 0 4 &mpic 3 1 0 0
|
||||
>;
|
||||
ranges = <0x2000000 0x0 0xc0000000
|
||||
0x2000000 0x0 0xc0000000
|
||||
|
|
@ -467,38 +161,22 @@
|
|||
};
|
||||
};
|
||||
|
||||
pci1: pcie@ff609000 {
|
||||
compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
|
||||
cell-index = <2>;
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
board_pci1: pci1: pcie@ff609000 {
|
||||
reg = <0 0xff609000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
|
||||
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
pcie@0 {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
/*
|
||||
* IRQ[4:6] only for PCIe, set to active-high,
|
||||
* IRQ[7] is pulled up on board, set to active-low
|
||||
*/
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 4 2
|
||||
0000 0 0 2 &mpic 5 2
|
||||
0000 0 0 3 &mpic 6 2
|
||||
0000 0 0 4 &mpic 7 1
|
||||
0000 0 0 1 &mpic 4 2 0 0
|
||||
0000 0 0 2 &mpic 5 2 0 0
|
||||
0000 0 0 3 &mpic 6 2 0 0
|
||||
0000 0 0 4 &mpic 7 1 0 0
|
||||
>;
|
||||
ranges = <0x2000000 0x0 0xa0000000
|
||||
0x2000000 0x0 0xa0000000
|
||||
|
|
@ -511,37 +189,21 @@
|
|||
};
|
||||
|
||||
pci2: pcie@ff60b000 {
|
||||
cell-index = <3>;
|
||||
compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xff60b000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
|
||||
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
pcie@0 {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
/*
|
||||
* IRQ[8:10] are pulled up on board, set to active-low
|
||||
* IRQ[11] only for PCIe, set to active-high,
|
||||
*/
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 8 1
|
||||
0000 0 0 2 &mpic 9 1
|
||||
0000 0 0 3 &mpic 10 1
|
||||
0000 0 0 4 &mpic 11 2
|
||||
0000 0 0 1 &mpic 8 1 0 0
|
||||
0000 0 0 2 &mpic 9 1 0 0
|
||||
0000 0 0 3 &mpic 10 1 0 0
|
||||
0000 0 0 4 &mpic 11 2 0 0
|
||||
>;
|
||||
ranges = <0x2000000 0x0 0x80000000
|
||||
0x2000000 0x0 0x80000000
|
||||
|
|
@ -553,3 +215,5 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "fsl/p1023si-post.dtsi"
|
||||
|
|
|
|||
Loading…
Reference in New Issue