clk: stm32mp1: Add ddrperfm clock
Add ddrperfm clock for DDR Performance Monitor driver Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Gerald Baeza <gerald.baeza@st.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -1402,6 +1402,7 @@ enum {
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G_CRYP1,
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G_CRYP1,
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G_HASH1,
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G_HASH1,
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G_BKPSRAM,
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G_BKPSRAM,
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G_DDRPERFM,
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G_LAST
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G_LAST
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};
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};
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@ -1488,6 +1489,7 @@ static struct stm32_gate_cfg per_gate_cfg[G_LAST] = {
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K_GATE(G_STGENRO, RCC_APB4ENSETR, 20, 0),
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K_GATE(G_STGENRO, RCC_APB4ENSETR, 20, 0),
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K_MGATE(G_USBPHY, RCC_APB4ENSETR, 16, 0),
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K_MGATE(G_USBPHY, RCC_APB4ENSETR, 16, 0),
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K_GATE(G_IWDG2, RCC_APB4ENSETR, 15, 0),
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K_GATE(G_IWDG2, RCC_APB4ENSETR, 15, 0),
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K_GATE(G_DDRPERFM, RCC_APB4ENSETR, 8, 0),
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K_MGATE(G_DSI, RCC_APB4ENSETR, 4, 0),
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K_MGATE(G_DSI, RCC_APB4ENSETR, 4, 0),
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K_MGATE(G_LTDC, RCC_APB4ENSETR, 0, 0),
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K_MGATE(G_LTDC, RCC_APB4ENSETR, 0, 0),
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@ -1899,6 +1901,7 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
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PCLK(CRC1, "crc1", "ck_axi", 0, G_CRC1),
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PCLK(CRC1, "crc1", "ck_axi", 0, G_CRC1),
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PCLK(USBH, "usbh", "ck_axi", 0, G_USBH),
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PCLK(USBH, "usbh", "ck_axi", 0, G_USBH),
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PCLK(ETHSTP, "ethstp", "ck_axi", 0, G_ETHSTP),
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PCLK(ETHSTP, "ethstp", "ck_axi", 0, G_ETHSTP),
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PCLK(DDRPERFM, "ddrperfm", "pclk4", 0, G_DDRPERFM),
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/* Kernel clocks */
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/* Kernel clocks */
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KCLK(SDMMC1_K, "sdmmc1_k", sdmmc12_src, 0, G_SDMMC1, M_SDMMC12),
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KCLK(SDMMC1_K, "sdmmc1_k", sdmmc12_src, 0, G_SDMMC1, M_SDMMC12),
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