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arm64: dts: Add PCIe node for APM X-Gene v2 platforms 

This patch adds PCIe node to support PCIe controller with MSI
capability for APM X-Gene v2 platform.

Signed-off-by: Duc Dang <dhdang@apm.com>
This commit is contained in:
Duc Dang 2015-10-12 16:09:17 -07:00
parent 726e92fdba
commit b055e9de9a
1 changed files with 59 additions and 0 deletions
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59
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
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@ -258,6 +258,15 @@
clock-output-names = "pcie0clk";
};
pcie1clk: pcie1clk@1f2cc000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
reg = <0x0 0x1f2cc000 0x0 0x1000>;
reg-names = "csr-reg";
clock-output-names = "pcie1clk";
};
xge0clk: xge0clk@1f61c000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
@ -316,6 +325,56 @@
interrupts = <0x0 0x4c 0x4>;
};
pcie0: pcie@1f2b0000 {
status = "disabled";
device_type = "pci";
compatible = "apm,xgene-pcie", "apm,xgene2-pcie";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
0xc0 0xd0000000 0x0 0x00040000>; /* PCI config space */
reg-names = "csr", "cfg";
ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */
0x02000000 0x00 0x20000000 0xc1 0x20000000 0x00 0x20000000 /* mem */
0x43000000 0xe0 0x00000000 0xe0 0x00000000 0x20 0x00000000>; /* mem */
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x1
0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x11 0x1
0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x12 0x1
0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x13 0x1>;
dma-coherent;
clocks = <&pcie0clk 0>;
msi-parent = <&v2m0>;
};
pcie1: pcie@1f2c0000 {
status = "disabled";
device_type = "pci";
compatible = "apm,xgene-pcie", "apm,xgene2-pcie";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */
0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
reg-names = "csr", "cfg";
ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */
0x02000000 0x00 0x20000000 0xa1 0x20000000 0x00 0x20000000 /* mem */
0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x1
0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x17 0x1
0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x18 0x1
0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x19 0x1>;
dma-coherent;
clocks = <&pcie1clk 0>;
msi-parent = <&v2m0>;
};
sata1: sata@1a000000 {
compatible = "apm,xgene-ahci";
reg = <0x0 0x1a000000 0x0 0x1000>,