ARM: dts: imx6sl: move GIC to right location in DT
GIC is inside of SoC from architecture perspective, it should be located inside of soc node in DT. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
parent
211ded7861
commit
b051589c69
|
@ -77,15 +77,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
intc: interrupt-controller@a01000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x00a01000 0x1000>,
|
||||
<0x00a00100 0x100>;
|
||||
interrupt-parent = <&intc>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
ckil {
|
||||
compatible = "fixed-clock";
|
||||
|
@ -133,6 +124,15 @@
|
|||
clocks = <&clks IMX6SL_CLK_OCRAM>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@a01000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x00a01000 0x1000>,
|
||||
<0x00a00100 0x100>;
|
||||
interrupt-parent = <&intc>;
|
||||
};
|
||||
|
||||
L2: l2-cache@a02000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x00a02000 0x1000>;
|
||||
|
|
Loading…
Reference in New Issue