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staging: rtl8723au: phy_SsPwrSwitch92CU() was never called with bRegSSPwrLvl != 1 

Get rid of the alternate code paths since these weren't used and have
never been tested according to the in-code comments.

Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Jes Sorensen 2014-11-30 16:05:06 -05:00 committed by Greg Kroah-Hartman
parent 0e316c2251
commit b024793188
1 changed files with 78 additions and 232 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

310
drivers/staging/rtl8723au/hal/usb_halinit.c
View File

@ -26,8 +26,7 @@
#include <usb_ops.h> #include <usb_ops.h>
static void phy_SsPwrSwitch92CU(struct rtw_adapter *Adapter, static void phy_SsPwrSwitch92CU(struct rtw_adapter *Adapter,
enum rt_rf_power_state eRFPowerState, enum rt_rf_power_state eRFPowerState);
int bRegSSPwrLvl);
static void static void
_ConfigChipOutEP(struct rtw_adapter *pAdapter, u8 NumOutPipe) _ConfigChipOutEP(struct rtw_adapter *pAdapter, u8 NumOutPipe)
@ -513,9 +512,7 @@ int rtl8723au_hal_init(struct rtw_adapter *Adapter)
Adapter->hw_init_completed = false; Adapter->hw_init_completed = false;
if (Adapter->pwrctrlpriv.bkeepfwalive) { if (Adapter->pwrctrlpriv.bkeepfwalive) {
/* here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2 phy_SsPwrSwitch92CU(Adapter, rf_on);
needs to be verified */
phy_SsPwrSwitch92CU(Adapter, rf_on, 1);
if (pHalData->bIQKInitialized) { if (pHalData->bIQKInitialized) {
rtl8723a_phy_iq_calibrate(Adapter, true); rtl8723a_phy_iq_calibrate(Adapter, true);
@ -776,112 +773,50 @@ exit:
} }
static void phy_SsPwrSwitch92CU(struct rtw_adapter *Adapter, static void phy_SsPwrSwitch92CU(struct rtw_adapter *Adapter,
enum rt_rf_power_state eRFPowerState, enum rt_rf_power_state eRFPowerState)
int bRegSSPwrLvl)
{ {
struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
u8 value8, sps0; u8 sps0;
u8 bytetmp;
sps0 = rtl8723au_read8(Adapter, REG_SPS0_CTRL); sps0 = rtl8723au_read8(Adapter, REG_SPS0_CTRL);
switch (eRFPowerState) { switch (eRFPowerState) {
case rf_on: case rf_on:
if (bRegSSPwrLvl == 1) { /* 1. Enable MAC Clock. Can not be enabled now. */
/* 1. Enable MAC Clock. Can not be enabled now. */ /* WriteXBYTE(REG_SYS_CLKR+1,
/* WriteXBYTE(REG_SYS_CLKR+1, ReadXBYTE(REG_SYS_CLKR+1) | BIT(3)); */
ReadXBYTE(REG_SYS_CLKR+1) | BIT(3)); */
/* 2. Force PWM, Enable SPS18_LDO_Marco_Block */ /* 2. Force PWM, Enable SPS18_LDO_Marco_Block */
rtl8723au_write8(Adapter, REG_SPS0_CTRL, rtl8723au_write8(Adapter, REG_SPS0_CTRL,
sps0 | BIT(0) | BIT(3)); sps0 | BIT(0) | BIT(3));
/* 3. restore BB, AFE control register. */ /* 3. restore BB, AFE control register. */
/* RF */ /* RF */
if (pHalData->rf_type == RF_2T2R) if (pHalData->rf_type == RF_2T2R)
PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
0x380038, 1); 0x380038, 1);
else else
PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
0x38, 1); 0x38, 1);
PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 1); PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 1);
PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(1), 0); PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(1), 0);
/* AFE */ /* AFE */
if (pHalData->rf_type == RF_2T2R) if (pHalData->rf_type == RF_2T2R)
PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord, PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord,
0x63DB25A0); 0x63DB25A0);
else if (pHalData->rf_type == RF_1T1R) else if (pHalData->rf_type == RF_1T1R)
PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord, PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord,
0x631B25A0); 0x631B25A0);
/* 4. issue 3-wire command that RF set to Rx idle /* 4. issue 3-wire command that RF set to Rx idle
mode. This is used to re-write the RX idle mode. */ mode. This is used to re-write the RX idle mode. */
/* We can only prvide a usual value instead and then /* We can only prvide a usual value instead and then
HW will modify the value by itself. */ HW will modify the value by itself. */
PHY_SetRFReg(Adapter, RF_PATH_A, 0, PHY_SetRFReg(Adapter, RF_PATH_A, 0, bRFRegOffsetMask, 0x32D95);
if (pHalData->rf_type == RF_2T2R) {
PHY_SetRFReg(Adapter, RF_PATH_B, 0,
bRFRegOffsetMask, 0x32D95); bRFRegOffsetMask, 0x32D95);
if (pHalData->rf_type == RF_2T2R) {
PHY_SetRFReg(Adapter, RF_PATH_B, 0,
bRFRegOffsetMask, 0x32D95);
}
} else { /* Level 2 or others. */
/* h. AFE_PLL_CTRL 0x28[7:0] = 0x80
disable AFE PLL */
rtl8723au_write8(Adapter, REG_AFE_PLL_CTRL, 0x81);
/* i. AFE_XTAL_CTRL 0x24[15:0] = 0x880F
gated AFE DIG_CLOCK */
rtl8723au_write16(Adapter, REG_AFE_XTAL_CTRL, 0x800F);
mdelay(1);
/* 2. Force PWM, Enable SPS18_LDO_Marco_Block */
rtl8723au_write8(Adapter, REG_SPS0_CTRL,
sps0 | BIT(0) | BIT(3));
/* 3. restore BB, AFE control register. */
/* RF */
if (pHalData->rf_type == RF_2T2R)
PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
0x380038, 1);
else
PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
0x38, 1);
PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 1);
PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(1), 0);
/* AFE */
if (pHalData->rf_type == RF_2T2R)
PHY_SetBBReg(Adapter, rRx_Wait_CCA,
bMaskDWord, 0x63DB25A0);
else if (pHalData->rf_type == RF_1T1R)
PHY_SetBBReg(Adapter, rRx_Wait_CCA,
bMaskDWord, 0x631B25A0);
/* 4. issue 3-wire command that RF set to Rx idle
mode. This is used to re-write the RX idle mode. */
/* We can only prvide a usual value instead and
then HW will modify the value by itself. */
PHY_SetRFReg(Adapter, RF_PATH_A, 0,
bRFRegOffsetMask, 0x32D95);
if (pHalData->rf_type == RF_2T2R) {
PHY_SetRFReg(Adapter, RF_PATH_B, 0,
bRFRegOffsetMask, 0x32D95);
}
/* 5. gated MAC Clock */
bytetmp = rtl8723au_read8(Adapter, REG_APSD_CTRL);
rtl8723au_write8(Adapter, REG_APSD_CTRL,
bytetmp & ~BIT(6));
mdelay(10);
/* Set BB reset at first */
/* 0x16 */
rtl8723au_write8(Adapter, REG_SYS_FUNC_EN, 0x17);
/* Enable TX */
rtl8723au_write8(Adapter, REG_TXPAUSE, 0x0);
} }
break; break;
case rf_sleep: case rf_sleep:
@ -890,146 +825,57 @@ static void phy_SsPwrSwitch92CU(struct rtw_adapter *Adapter,
sps0 &= ~BIT(0); sps0 &= ~BIT(0);
else else
sps0 &= ~(BIT(0) | BIT(3)); sps0 &= ~(BIT(0) | BIT(3));
if (bRegSSPwrLvl == 1) {
RT_TRACE(_module_hal_init_c_, _drv_err_, ("SS LVL1\n"));
/* Disable RF and BB only for SelectSuspend. */
/* 1. Set BB/RF to shutdown. */ RT_TRACE(_module_hal_init_c_, _drv_err_, ("SS LVL1\n"));
/* (1) Reg878[5:3]= 0 RF rx_code for /* Disable RF and BB only for SelectSuspend. */
preamble power saving */
/* (2)Reg878[21:19]= 0 Turn off RF-B */
/* (3) RegC04[7:4]= 0 Turn off all paths
for packet detection */
/* (4) Reg800[1] = 1 enable preamble power
saving */
Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF0] =
PHY_QueryBBReg(Adapter, rFPGA0_XAB_RFParameter,
bMaskDWord);
Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF1] =
PHY_QueryBBReg(Adapter, rOFDM0_TRxPathEnable,
bMaskDWord);
Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF2] =
PHY_QueryBBReg(Adapter, rFPGA0_RFMOD,
bMaskDWord);
if (pHalData->rf_type == RF_2T2R) {
PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
0x380038, 0);
} else if (pHalData->rf_type == RF_1T1R) {
PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
0x38, 0);
}
PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 0);
PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(1), 1);
/* 2 .AFE control register to power down. bit[30:22] */ /* 1. Set BB/RF to shutdown. */
Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_AFE0] = /* (1) Reg878[5:3]= 0 RF rx_code for
PHY_QueryBBReg(Adapter, rRx_Wait_CCA, preamble power saving */
bMaskDWord); /* (2)Reg878[21:19]= 0 Turn off RF-B */
if (pHalData->rf_type == RF_2T2R) /* (3) RegC04[7:4]= 0 Turn off all paths
PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord, for packet detection */
0x00DB25A0); /* (4) Reg800[1] = 1 enable preamble power saving */
else if (pHalData->rf_type == RF_1T1R) Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF0] =
PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord, PHY_QueryBBReg(Adapter, rFPGA0_XAB_RFParameter,
0x001B25A0); bMaskDWord);
Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF1] =
/* 3. issue 3-wire command that RF set to power down.*/ PHY_QueryBBReg(Adapter, rOFDM0_TRxPathEnable,
PHY_SetRFReg(Adapter, RF_PATH_A, 0, bRFRegOffsetMask, 0); bMaskDWord);
if (pHalData->rf_type == RF_2T2R) Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF2] =
PHY_SetRFReg(Adapter, RF_PATH_B, 0, PHY_QueryBBReg(Adapter, rFPGA0_RFMOD, bMaskDWord);
bRFRegOffsetMask, 0); if (pHalData->rf_type == RF_2T2R) {
PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
/* 4. Force PFM , disable SPS18_LDO_Marco_Block */ 0x380038, 0);
rtl8723au_write8(Adapter, REG_SPS0_CTRL, sps0); } else if (pHalData->rf_type == RF_1T1R) {
} else { /* Level 2 or others. */ PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x38, 0);
RT_TRACE(_module_hal_init_c_, _drv_err_, ("SS LVL2\n"));
{
u8 eRFPath = RF_PATH_A, value8 = 0;
rtl8723au_write8(Adapter, REG_TXPAUSE, 0xFF);
PHY_SetRFReg(Adapter,
(enum RF_RADIO_PATH)eRFPath,
0x0, bMaskByte0, 0x0);
value8 |= APSDOFF;
/* 0x40 */
rtl8723au_write8(Adapter, REG_APSD_CTRL,
value8);
/* After switch APSD, we need to delay
for stability */
mdelay(10);
/* Set BB reset at first */
value8 = 0;
value8 |= (FEN_USBD | FEN_USBA |
FEN_BB_GLB_RSTn);
/* 0x16 */
rtl8723au_write8(Adapter, REG_SYS_FUNC_EN,
value8);
}
/* Disable RF and BB only for SelectSuspend. */
/* 1. Set BB/RF to shutdown. */
/* (1) Reg878[5:3]= 0 RF rx_code for
preamble power saving */
/* (2)Reg878[21:19]= 0 Turn off RF-B */
/* (3) RegC04[7:4]= 0 Turn off all paths for
packet detection */
/* (4) Reg800[1] = 1 enable preamble power
saving */
Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF0] =
PHY_QueryBBReg(Adapter, rFPGA0_XAB_RFParameter,
bMaskDWord);
Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF1] =
PHY_QueryBBReg(Adapter, rOFDM0_TRxPathEnable,
bMaskDWord);
Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF2] =
PHY_QueryBBReg(Adapter, rFPGA0_RFMOD,
bMaskDWord);
if (pHalData->rf_type == RF_2T2R)
PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
0x380038, 0);
else if (pHalData->rf_type == RF_1T1R)
PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
0x38, 0);
PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 0);
PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(1), 1);
/* 2 .AFE control register to power down. bit[30:22] */
Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_AFE0] =
PHY_QueryBBReg(Adapter, rRx_Wait_CCA,
bMaskDWord);
if (pHalData->rf_type == RF_2T2R)
PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord,
0x00DB25A0);
else if (pHalData->rf_type == RF_1T1R)
PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord,
0x001B25A0);
/* 3. issue 3-wire command that RF set to power down. */
PHY_SetRFReg(Adapter, RF_PATH_A, 0, bRFRegOffsetMask, 0);
if (pHalData->rf_type == RF_2T2R)
PHY_SetRFReg(Adapter, RF_PATH_B, 0,
bRFRegOffsetMask, 0);
/* 4. Force PFM , disable SPS18_LDO_Marco_Block */
rtl8723au_write8(Adapter, REG_SPS0_CTRL, sps0);
/* 2010/10/13 MH/Isaachsu exchange sequence. */
/* h. AFE_PLL_CTRL 0x28[7:0] = 0x80
disable AFE PLL */
rtl8723au_write8(Adapter, REG_AFE_PLL_CTRL, 0x80);
mdelay(1);
/* i. AFE_XTAL_CTRL 0x24[15:0] = 0x880F
gated AFE DIG_CLOCK */
rtl8723au_write16(Adapter, REG_AFE_XTAL_CTRL, 0xA80F);
} }
PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 0);
PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(1), 1);
/* 2 .AFE control register to power down. bit[30:22] */
Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_AFE0] =
PHY_QueryBBReg(Adapter, rRx_Wait_CCA, bMaskDWord);
if (pHalData->rf_type == RF_2T2R)
PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord,
0x00DB25A0);
else if (pHalData->rf_type == RF_1T1R)
PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord,
0x001B25A0);
/* 3. issue 3-wire command that RF set to power down.*/
PHY_SetRFReg(Adapter, RF_PATH_A, 0, bRFRegOffsetMask, 0);
if (pHalData->rf_type == RF_2T2R)
PHY_SetRFReg(Adapter, RF_PATH_B, 0,
bRFRegOffsetMask, 0);
/* 4. Force PFM , disable SPS18_LDO_Marco_Block */
rtl8723au_write8(Adapter, REG_SPS0_CTRL, sps0);
break; break;
default: default:
break; break;
} }
}
} /* phy_PowerSwitch92CU */
static void CardDisableRTL8723U(struct rtw_adapter *Adapter) static void CardDisableRTL8723U(struct rtw_adapter *Adapter)
{ {