drm/i915/gvt: Refactor GVT vblank emulator for vGPU virtual display
Current vblank emulator uses single hrtimer at 16ms period for all vGPUs, which introduces three major issues: - 16ms matches the refresh rate at 62.5Hz (instead of 60Hz) which doesn't follow standard timing. This leads to some frame drop or glitch issue during video playback. SW expects a vsync interval of 16.667ms or higher precision for an accurate 60Hz refresh rate. However current vblank emulator only works at 16ms. - Doesn't respect the fact that with current virtual EDID timing set, not all resolutions are running at 60Hz. For example, current virtual EDID also supports refresh rate at 56Hz, 59.97Hz, 60Hz, 75Hz, etc. - Current vblank emulator use single hrtimer for all vGPUs. Regardsless the possibility that different guests could run in different resolutions, all vsync interrupts are injected at 16ms interval with same hrtimer. Based on previous patch which decode guest expected refresh rate from vreg, the vblank emulator refactor patch makes following changes: - Change the vblank emulator hrtimer from gvt global to per-vGPU. By doing this, each vGPU display can operates at different refresh rates. Currently only one dislay is supported for each vGPU so per-vGPU hrtimer is enough. If multiple displays are supported per-vGPU in future, we can expand to per-PIPE further. - Change the fixed hrtimer period from 16ms to dynamic based on vreg. GVT is expected to emulate the HW as close as possible. So reflacting the accurate vsync interrupt interval is more correct than fixed 16ms. - Change the vblank timer period and start the timer on PIPECONF change. The initial period is updated to 16666667 based on 60Hz refresh rate. According to PRM, PIPECONF controls the timing generator of the connected display on this pipe, so it's safe to stop hrtimer on PIPECONF disabling, and re-start hrtimer at new period on enabling. Other changes including: - Move vblank_timer_fn from irq.c into display.c. - Clean per-vGPU vblank timer at clean_display instead of clean_irq. To run quick test, launch a web browser and goto URL: www.displayhz.com The actual refresh rate from guest can now always match guest settings. V2: Rebase to 5.11. Remove unused intel_gvt_clean_irq(). Simplify enable logic in update_vblank_emulation(). (zhenyu) Loop all vGPU by idr when check all vblank timer. (zhenyu) Signed-off-by: Colin Xu <colin.xu@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20210226044630.284269-1-colin.xu@intel.com Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>
This commit is contained in:
Colin Xu
Zhenyu Wang
parent
6a4500c7b8
commit
b01739fb86
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@ -501,11 +501,27 @@ static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
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port->dpcd = NULL;
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}
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static enum hrtimer_restart vblank_timer_fn(struct hrtimer *data)
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{
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struct intel_vgpu_vblank_timer *vblank_timer;
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struct intel_vgpu *vgpu;
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vblank_timer = container_of(data, struct intel_vgpu_vblank_timer, timer);
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vgpu = container_of(vblank_timer, struct intel_vgpu, vblank_timer);
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/* Set vblank emulation request per-vGPU bit */
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intel_gvt_request_service(vgpu->gvt,
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INTEL_GVT_REQUEST_EMULATE_VBLANK + vgpu->id);
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hrtimer_add_expires_ns(&vblank_timer->timer, vblank_timer->period);
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return HRTIMER_RESTART;
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}
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static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
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int type, unsigned int resolution)
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{
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struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
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struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
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struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer;
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if (drm_WARN_ON(&i915->drm, resolution >= GVT_EDID_NUM))
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return -EINVAL;
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@ -532,47 +548,56 @@ static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
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port->vrefresh_k = GVT_DEFAULT_REFRESH_RATE * MSEC_PER_SEC;
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vgpu->display.port_num = port_num;
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/* Init hrtimer based on default refresh rate */
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hrtimer_init(&vblank_timer->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
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vblank_timer->timer.function = vblank_timer_fn;
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vblank_timer->vrefresh_k = port->vrefresh_k;
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vblank_timer->period = DIV64_U64_ROUND_CLOSEST(NSEC_PER_SEC * MSEC_PER_SEC, vblank_timer->vrefresh_k);
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emulate_monitor_status_change(vgpu);
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return 0;
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}
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/**
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* intel_gvt_check_vblank_emulation - check if vblank emulation timer should
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* be turned on/off when a virtual pipe is enabled/disabled.
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* @gvt: a GVT device
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* vgpu_update_vblank_emulation - Update per-vGPU vblank_timer
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* @vgpu: vGPU operated
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* @turnon: Turn ON/OFF vblank_timer
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*
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* This function is used to turn on/off vblank timer according to currently
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* enabled/disabled virtual pipes.
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* This function is used to turn on/off or update the per-vGPU vblank_timer
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* when PIPECONF is enabled or disabled. vblank_timer period is also updated
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* if guest changed the refresh rate.
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*
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*/
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void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt)
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void vgpu_update_vblank_emulation(struct intel_vgpu *vgpu, bool turnon)
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{
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struct intel_gvt_irq *irq = &gvt->irq;
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struct intel_vgpu *vgpu;
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int pipe, id;
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int found = false;
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struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer;
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struct intel_vgpu_port *port =
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intel_vgpu_port(vgpu, vgpu->display.port_num);
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mutex_lock(&gvt->lock);
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for_each_active_vgpu(gvt, vgpu, id) {
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for (pipe = 0; pipe < I915_MAX_PIPES; pipe++) {
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if (pipe_is_enabled(vgpu, pipe)) {
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found = true;
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break;
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}
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if (turnon) {
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/*
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* Skip the re-enable if already active and vrefresh unchanged.
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* Otherwise, stop timer if already active and restart with new
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* period.
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*/
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if (vblank_timer->vrefresh_k != port->vrefresh_k ||
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!hrtimer_active(&vblank_timer->timer)) {
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/* Stop timer before start with new period if active */
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if (hrtimer_active(&vblank_timer->timer))
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hrtimer_cancel(&vblank_timer->timer);
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/* Make sure new refresh rate updated to timer period */
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vblank_timer->vrefresh_k = port->vrefresh_k;
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vblank_timer->period = DIV64_U64_ROUND_CLOSEST(NSEC_PER_SEC * MSEC_PER_SEC, vblank_timer->vrefresh_k);
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hrtimer_start(&vblank_timer->timer,
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ktime_add_ns(ktime_get(), vblank_timer->period),
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HRTIMER_MODE_ABS);
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}
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if (found)
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break;
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} else {
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/* Caller request to stop vblank */
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hrtimer_cancel(&vblank_timer->timer);
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}
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/* all the pipes are disabled */
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if (!found)
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hrtimer_cancel(&irq->vblank_timer.timer);
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else
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hrtimer_start(&irq->vblank_timer.timer,
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ktime_add_ns(ktime_get(), irq->vblank_timer.period),
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HRTIMER_MODE_ABS);
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mutex_unlock(&gvt->lock);
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}
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static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)
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@ -604,7 +629,7 @@ static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)
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}
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}
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static void emulate_vblank(struct intel_vgpu *vgpu)
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void intel_vgpu_emulate_vblank(struct intel_vgpu *vgpu)
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{
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int pipe;
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@ -614,24 +639,6 @@ static void emulate_vblank(struct intel_vgpu *vgpu)
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mutex_unlock(&vgpu->vgpu_lock);
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}
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/**
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* intel_gvt_emulate_vblank - trigger vblank events for vGPUs on GVT device
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* @gvt: a GVT device
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*
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* This function is used to trigger vblank interrupts for vGPUs on GVT device
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*
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*/
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void intel_gvt_emulate_vblank(struct intel_gvt *gvt)
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{
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struct intel_vgpu *vgpu;
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int id;
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mutex_lock(&gvt->lock);
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for_each_active_vgpu(gvt, vgpu, id)
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emulate_vblank(vgpu);
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mutex_unlock(&gvt->lock);
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}
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/**
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* intel_vgpu_emulate_hotplug - trigger hotplug event for vGPU
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* @vgpu: a vGPU
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@ -722,6 +729,8 @@ void intel_vgpu_clean_display(struct intel_vgpu *vgpu)
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clean_virtual_dp_monitor(vgpu, PORT_D);
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else
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clean_virtual_dp_monitor(vgpu, PORT_B);
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vgpu_update_vblank_emulation(vgpu, false);
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}
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/**
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@ -36,6 +36,7 @@
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#define _GVT_DISPLAY_H_
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#include <linux/types.h>
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#include <linux/hrtimer.h>
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struct intel_gvt;
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struct intel_vgpu;
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@ -169,6 +170,12 @@ struct intel_vgpu_port {
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u32 vrefresh_k;
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};
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struct intel_vgpu_vblank_timer {
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struct hrtimer timer;
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u32 vrefresh_k;
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u64 period;
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};
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static inline char *vgpu_edid_str(enum intel_vgpu_edid id)
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{
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switch (id) {
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@ -205,8 +212,8 @@ static inline unsigned int vgpu_edid_yres(enum intel_vgpu_edid id)
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}
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}
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void intel_gvt_emulate_vblank(struct intel_gvt *gvt);
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void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt);
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void intel_vgpu_emulate_vblank(struct intel_vgpu *vgpu);
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void vgpu_update_vblank_emulation(struct intel_vgpu *vgpu, bool turnon);
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int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution);
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void intel_vgpu_reset_display(struct intel_vgpu *vgpu);
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@ -203,6 +203,22 @@ static void init_device_info(struct intel_gvt *gvt)
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info->msi_cap_offset = pdev->msi_cap;
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}
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static void intel_gvt_test_and_emulate_vblank(struct intel_gvt *gvt)
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{
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struct intel_vgpu *vgpu;
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int id;
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mutex_lock(&gvt->lock);
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idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) {
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if (test_and_clear_bit(INTEL_GVT_REQUEST_EMULATE_VBLANK + id,
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(void *)&gvt->service_request)) {
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if (vgpu->active)
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intel_vgpu_emulate_vblank(vgpu);
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}
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}
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mutex_unlock(&gvt->lock);
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}
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static int gvt_service_thread(void *data)
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{
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struct intel_gvt *gvt = (struct intel_gvt *)data;
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@ -220,9 +236,7 @@ static int gvt_service_thread(void *data)
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if (WARN_ONCE(ret, "service thread is waken up by signal.\n"))
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continue;
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if (test_and_clear_bit(INTEL_GVT_REQUEST_EMULATE_VBLANK,
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(void *)&gvt->service_request))
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intel_gvt_emulate_vblank(gvt);
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intel_gvt_test_and_emulate_vblank(gvt);
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if (test_bit(INTEL_GVT_REQUEST_SCHED,
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(void *)&gvt->service_request) ||
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@ -278,7 +292,6 @@ void intel_gvt_clean_device(struct drm_i915_private *i915)
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intel_gvt_clean_sched_policy(gvt);
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intel_gvt_clean_workload_scheduler(gvt);
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intel_gvt_clean_gtt(gvt);
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intel_gvt_clean_irq(gvt);
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intel_gvt_free_firmware(gvt);
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intel_gvt_clean_mmio_info(gvt);
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idr_destroy(&gvt->vgpu_idr);
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@ -337,7 +350,7 @@ int intel_gvt_init_device(struct drm_i915_private *i915)
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ret = intel_gvt_init_gtt(gvt);
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if (ret)
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goto out_clean_irq;
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goto out_free_firmware;
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ret = intel_gvt_init_workload_scheduler(gvt);
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if (ret)
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@ -392,8 +405,6 @@ out_clean_workload_scheduler:
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intel_gvt_clean_workload_scheduler(gvt);
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out_clean_gtt:
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intel_gvt_clean_gtt(gvt);
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out_clean_irq:
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intel_gvt_clean_irq(gvt);
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out_free_firmware:
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intel_gvt_free_firmware(gvt);
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out_clean_mmio_info:
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@ -215,6 +215,7 @@ struct intel_vgpu {
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struct list_head dmabuf_obj_list_head;
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struct mutex dmabuf_lock;
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struct idr object_idr;
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struct intel_vgpu_vblank_timer vblank_timer;
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u32 scan_nonprivbb;
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};
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@ -344,13 +345,16 @@ static inline struct intel_gvt *to_gvt(struct drm_i915_private *i915)
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}
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enum {
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INTEL_GVT_REQUEST_EMULATE_VBLANK = 0,
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/* Scheduling trigger by timer */
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INTEL_GVT_REQUEST_SCHED = 1,
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INTEL_GVT_REQUEST_SCHED = 0,
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/* Scheduling trigger by event */
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INTEL_GVT_REQUEST_EVENT_SCHED = 2,
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INTEL_GVT_REQUEST_EVENT_SCHED = 1,
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/* per-vGPU vblank emulation request */
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INTEL_GVT_REQUEST_EMULATE_VBLANK = 2,
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INTEL_GVT_REQUEST_EMULATE_VBLANK_MAX = INTEL_GVT_REQUEST_EMULATE_VBLANK
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+ GVT_MAX_VGPU,
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};
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static inline void intel_gvt_request_service(struct intel_gvt *gvt,
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@ -703,14 +703,11 @@ static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
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if (data & PIPECONF_ENABLE) {
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vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE;
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vgpu_update_refresh_rate(vgpu);
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vgpu_update_vblank_emulation(vgpu, true);
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} else {
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vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE;
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vgpu_update_vblank_emulation(vgpu, false);
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}
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/* vgpu_lock already hold by emulate mmio r/w */
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mutex_unlock(&vgpu->vgpu_lock);
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intel_gvt_check_vblank_emulation(vgpu->gvt);
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mutex_lock(&vgpu->vgpu_lock);
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return 0;
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}
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@ -647,38 +647,6 @@ static void init_events(
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}
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}
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static enum hrtimer_restart vblank_timer_fn(struct hrtimer *data)
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{
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struct intel_gvt_vblank_timer *vblank_timer;
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struct intel_gvt_irq *irq;
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struct intel_gvt *gvt;
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vblank_timer = container_of(data, struct intel_gvt_vblank_timer, timer);
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irq = container_of(vblank_timer, struct intel_gvt_irq, vblank_timer);
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gvt = container_of(irq, struct intel_gvt, irq);
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intel_gvt_request_service(gvt, INTEL_GVT_REQUEST_EMULATE_VBLANK);
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hrtimer_add_expires_ns(&vblank_timer->timer, vblank_timer->period);
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return HRTIMER_RESTART;
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}
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/**
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* intel_gvt_clean_irq - clean up GVT-g IRQ emulation subsystem
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* @gvt: a GVT device
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*
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* This function is called at driver unloading stage, to clean up GVT-g IRQ
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* emulation subsystem.
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*
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*/
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void intel_gvt_clean_irq(struct intel_gvt *gvt)
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{
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struct intel_gvt_irq *irq = &gvt->irq;
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hrtimer_cancel(&irq->vblank_timer.timer);
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}
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#define VBLANK_TIMER_PERIOD 16000000
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/**
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* intel_gvt_init_irq - initialize GVT-g IRQ emulation subsystem
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* @gvt: a GVT device
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@ -692,7 +660,6 @@ void intel_gvt_clean_irq(struct intel_gvt *gvt)
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int intel_gvt_init_irq(struct intel_gvt *gvt)
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{
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struct intel_gvt_irq *irq = &gvt->irq;
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struct intel_gvt_vblank_timer *vblank_timer = &irq->vblank_timer;
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gvt_dbg_core("init irq framework\n");
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@ -707,9 +674,5 @@ int intel_gvt_init_irq(struct intel_gvt *gvt)
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init_irq_map(irq);
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hrtimer_init(&vblank_timer->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
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vblank_timer->timer.function = vblank_timer_fn;
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vblank_timer->period = VBLANK_TIMER_PERIOD;
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return 0;
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}
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@ -201,11 +201,6 @@ struct intel_gvt_irq_map {
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u32 down_irq_bitmask;
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};
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struct intel_gvt_vblank_timer {
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struct hrtimer timer;
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u64 period;
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};
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/* structure containing device specific IRQ state */
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struct intel_gvt_irq {
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struct intel_gvt_irq_ops *ops;
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@ -214,11 +209,9 @@ struct intel_gvt_irq {
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struct intel_gvt_event_info events[INTEL_GVT_EVENT_MAX];
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DECLARE_BITMAP(pending_events, INTEL_GVT_EVENT_MAX);
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struct intel_gvt_irq_map *irq_map;
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struct intel_gvt_vblank_timer vblank_timer;
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};
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int intel_gvt_init_irq(struct intel_gvt *gvt);
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void intel_gvt_clean_irq(struct intel_gvt *gvt);
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void intel_vgpu_trigger_virtual_event(struct intel_vgpu *vgpu,
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enum intel_gvt_event_type event);
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@ -300,8 +300,6 @@ void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu)
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mutex_unlock(&vgpu->vgpu_lock);
|
||||
|
||||
mutex_lock(&gvt->lock);
|
||||
if (idr_is_empty(&gvt->vgpu_idr))
|
||||
intel_gvt_clean_irq(gvt);
|
||||
intel_gvt_update_vgpu_types(gvt);
|
||||
mutex_unlock(&gvt->lock);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue