phy: Add RGMII support on lan966x
The serdes driver contains also a mux to decide which interface type to use. Currently the driver supports GMII/SGMII/QSGMII and partially RGMII. As it doesn't support all the other RGMII interfaces like RGMII_TXID/RXID/ID and it could run only at 1G. Therefore extend this for all the other speeds(10/100) and also allow the other interfaces. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Link: https://lore.kernel.org/r/20220901121455.245103-1-horatiu.vultur@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Horatiu Vultur
Vinod Koul
parent
f340ed8664
commit
b013110733
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@ -42,7 +42,10 @@
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#define SERDES_MUX_QSGMII(i, p, m, c) \
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SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_QSGMII, m, c)
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#define SERDES_MUX_RGMII(i, p, m, c) \
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SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_RGMII, m, c)
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SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_RGMII, m, c), \
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SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_RGMII_TXID, m, c), \
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SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_RGMII_RXID, m, c), \
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SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_RGMII_ID, m, c)
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static void lan_rmw_(u32 val, u32 mask, void __iomem *mem, u32 offset)
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{
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@ -94,21 +97,29 @@ static const struct serdes_mux lan966x_serdes_muxes[] = {
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HSIO_HW_CFG_SD6G_1_CFG_SET(1)),
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SERDES_MUX_RGMII(RGMII(0), 2, HSIO_HW_CFG_RGMII_0_CFG |
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HSIO_HW_CFG_RGMII_ENA,
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HSIO_HW_CFG_RGMII_0_CFG_SET(BIT(0)) |
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HSIO_HW_CFG_RGMII_ENA_SET(BIT(0))),
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HSIO_HW_CFG_RGMII_ENA |
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HSIO_HW_CFG_GMII_ENA,
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HSIO_HW_CFG_RGMII_0_CFG_SET(0) |
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HSIO_HW_CFG_RGMII_ENA_SET(BIT(0)) |
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HSIO_HW_CFG_GMII_ENA_SET(BIT(2))),
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SERDES_MUX_RGMII(RGMII(1), 3, HSIO_HW_CFG_RGMII_1_CFG |
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HSIO_HW_CFG_RGMII_ENA,
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HSIO_HW_CFG_RGMII_1_CFG_SET(BIT(0)) |
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HSIO_HW_CFG_RGMII_ENA_SET(BIT(1))),
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HSIO_HW_CFG_RGMII_ENA |
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HSIO_HW_CFG_GMII_ENA,
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HSIO_HW_CFG_RGMII_1_CFG_SET(0) |
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HSIO_HW_CFG_RGMII_ENA_SET(BIT(1)) |
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HSIO_HW_CFG_GMII_ENA_SET(BIT(3))),
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SERDES_MUX_RGMII(RGMII(0), 5, HSIO_HW_CFG_RGMII_0_CFG |
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HSIO_HW_CFG_RGMII_ENA,
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HSIO_HW_CFG_RGMII_ENA |
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HSIO_HW_CFG_GMII_ENA,
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HSIO_HW_CFG_RGMII_0_CFG_SET(BIT(0)) |
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HSIO_HW_CFG_RGMII_ENA_SET(BIT(0))),
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HSIO_HW_CFG_RGMII_ENA_SET(BIT(0)) |
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HSIO_HW_CFG_GMII_ENA_SET(BIT(5))),
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SERDES_MUX_RGMII(RGMII(1), 6, HSIO_HW_CFG_RGMII_1_CFG |
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HSIO_HW_CFG_RGMII_ENA,
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HSIO_HW_CFG_RGMII_ENA |
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HSIO_HW_CFG_GMII_ENA,
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HSIO_HW_CFG_RGMII_1_CFG_SET(BIT(0)) |
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HSIO_HW_CFG_RGMII_ENA_SET(BIT(1))),
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HSIO_HW_CFG_RGMII_ENA_SET(BIT(1)) |
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HSIO_HW_CFG_GMII_ENA_SET(BIT(6))),
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};
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struct serdes_ctrl {
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@ -382,6 +393,67 @@ static int lan966x_sd6g40_setup(struct serdes_macro *macro, u32 idx, int mode)
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return lan966x_sd6g40_setup_lane(macro, conf, idx);
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}
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static int lan966x_rgmii_setup(struct serdes_macro *macro, u32 idx, int mode)
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{
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bool tx_delay = false;
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bool rx_delay = false;
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/* Configure RGMII */
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lan_rmw(HSIO_RGMII_CFG_RGMII_RX_RST_SET(0) |
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HSIO_RGMII_CFG_RGMII_TX_RST_SET(0) |
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HSIO_RGMII_CFG_TX_CLK_CFG_SET(macro->speed == SPEED_1000 ? 1 :
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macro->speed == SPEED_100 ? 2 :
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macro->speed == SPEED_10 ? 3 : 0),
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HSIO_RGMII_CFG_RGMII_RX_RST |
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HSIO_RGMII_CFG_RGMII_TX_RST |
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HSIO_RGMII_CFG_TX_CLK_CFG,
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macro->ctrl->regs, HSIO_RGMII_CFG(idx));
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if (mode == PHY_INTERFACE_MODE_RGMII ||
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mode == PHY_INTERFACE_MODE_RGMII_TXID)
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rx_delay = true;
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if (mode == PHY_INTERFACE_MODE_RGMII ||
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mode == PHY_INTERFACE_MODE_RGMII_RXID)
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tx_delay = true;
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/* Setup DLL configuration */
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lan_rmw(HSIO_DLL_CFG_DLL_RST_SET(0) |
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HSIO_DLL_CFG_DLL_ENA_SET(rx_delay),
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HSIO_DLL_CFG_DLL_RST |
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HSIO_DLL_CFG_DLL_ENA,
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macro->ctrl->regs, HSIO_DLL_CFG(idx == 0 ? 0x0 : 0x2));
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lan_rmw(HSIO_DLL_CFG_DELAY_ENA_SET(rx_delay),
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HSIO_DLL_CFG_DELAY_ENA,
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macro->ctrl->regs, HSIO_DLL_CFG(idx == 0 ? 0x0 : 0x2));
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lan_rmw(HSIO_DLL_CFG_DLL_RST_SET(0) |
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HSIO_DLL_CFG_DLL_ENA_SET(tx_delay),
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HSIO_DLL_CFG_DLL_RST |
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HSIO_DLL_CFG_DLL_ENA,
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macro->ctrl->regs, HSIO_DLL_CFG(idx == 0 ? 0x1 : 0x3));
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lan_rmw(HSIO_DLL_CFG_DELAY_ENA_SET(tx_delay),
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HSIO_DLL_CFG_DELAY_ENA,
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macro->ctrl->regs, HSIO_DLL_CFG(idx == 0 ? 0x1 : 0x3));
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return 0;
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}
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static int serdes_set_speed(struct phy *phy, int speed)
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{
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struct serdes_macro *macro = phy_get_drvdata(phy);
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if (!phy_interface_mode_is_rgmii(macro->mode))
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return 0;
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macro->speed = speed;
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lan966x_rgmii_setup(macro, macro->idx - (SERDES6G_MAX + 1), macro->mode);
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return 0;
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}
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static int serdes_set_mode(struct phy *phy, enum phy_mode mode, int submode)
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{
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struct serdes_macro *macro = phy_get_drvdata(phy);
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@ -424,7 +496,9 @@ static int serdes_set_mode(struct phy *phy, enum phy_mode mode, int submode)
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macro->mode);
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if (macro->idx < RGMII_MAX)
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return 0;
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return lan966x_rgmii_setup(macro,
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macro->idx - (SERDES6G_MAX + 1),
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macro->mode);
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return -EOPNOTSUPP;
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}
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@ -434,6 +508,7 @@ static int serdes_set_mode(struct phy *phy, enum phy_mode mode, int submode)
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static const struct phy_ops serdes_ops = {
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.set_mode = serdes_set_mode,
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.set_speed = serdes_set_speed,
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.owner = THIS_MODULE,
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};
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@ -206,4 +206,46 @@ enum lan966x_target {
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#define HSIO_HW_CFG_QSGMII_ENA_GET(x)\
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FIELD_GET(HSIO_HW_CFG_QSGMII_ENA, x)
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/* HSIO:HW_CFGSTAT:RGMII_CFG */
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#define HSIO_RGMII_CFG(r) __REG(TARGET_HSIO, 0, 1, 104, 0, 1, 52, 20, r, 2, 4)
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#define HSIO_RGMII_CFG_TX_CLK_CFG GENMASK(4, 2)
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#define HSIO_RGMII_CFG_TX_CLK_CFG_SET(x)\
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FIELD_PREP(HSIO_RGMII_CFG_TX_CLK_CFG, x)
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#define HSIO_RGMII_CFG_TX_CLK_CFG_GET(x)\
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FIELD_GET(HSIO_RGMII_CFG_TX_CLK_CFG, x)
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#define HSIO_RGMII_CFG_RGMII_TX_RST BIT(1)
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#define HSIO_RGMII_CFG_RGMII_TX_RST_SET(x)\
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FIELD_PREP(HSIO_RGMII_CFG_RGMII_TX_RST, x)
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#define HSIO_RGMII_CFG_RGMII_TX_RST_GET(x)\
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FIELD_GET(HSIO_RGMII_CFG_RGMII_TX_RST, x)
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#define HSIO_RGMII_CFG_RGMII_RX_RST BIT(0)
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#define HSIO_RGMII_CFG_RGMII_RX_RST_SET(x)\
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FIELD_PREP(HSIO_RGMII_CFG_RGMII_RX_RST, x)
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#define HSIO_RGMII_CFG_RGMII_RX_RST_GET(x)\
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FIELD_GET(HSIO_RGMII_CFG_RGMII_RX_RST, x)
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/* HSIO:HW_CFGSTAT:DLL_CFG */
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#define HSIO_DLL_CFG(r) __REG(TARGET_HSIO, 0, 1, 104, 0, 1, 52, 36, r, 4, 4)
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#define HSIO_DLL_CFG_DELAY_ENA BIT(2)
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#define HSIO_DLL_CFG_DELAY_ENA_SET(x)\
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FIELD_PREP(HSIO_DLL_CFG_DELAY_ENA, x)
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#define HSIO_DLL_CFG_DELAY_ENA_GET(x)\
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FIELD_GET(HSIO_DLL_CFG_DELAY_ENA, x)
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#define HSIO_DLL_CFG_DLL_ENA BIT(1)
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#define HSIO_DLL_CFG_DLL_ENA_SET(x)\
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FIELD_PREP(HSIO_DLL_CFG_DLL_ENA, x)
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#define HSIO_DLL_CFG_DLL_ENA_GET(x)\
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FIELD_GET(HSIO_DLL_CFG_DLL_ENA, x)
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#define HSIO_DLL_CFG_DLL_RST BIT(0)
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#define HSIO_DLL_CFG_DLL_RST_SET(x)\
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FIELD_PREP(HSIO_DLL_CFG_DLL_RST, x)
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#define HSIO_DLL_CFG_DLL_RST_GET(x)\
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FIELD_GET(HSIO_DLL_CFG_DLL_RST, x)
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#endif /* _LAN966X_HSIO_REGS_H_ */
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