clk: uniphier: add Pro4/Pro5/PXs2 audio system clock
Add clock for audio subsystem (AIO) on UniPhier Pro4/Pro5/PXs2 SoCs. Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -57,6 +57,14 @@
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#define UNIPHIER_PRO4_SYS_CLK_USB3(idx, ch) \
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UNIPHIER_CLK_GATE("usb3" #ch, (idx), NULL, 0x2104, 16 + (ch))
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#define UNIPHIER_PRO4_SYS_CLK_AIO(idx) \
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UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 8), \
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UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2104, 13)
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#define UNIPHIER_PRO5_SYS_CLK_AIO(idx) \
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UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 12), \
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UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2104, 13)
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#define UNIPHIER_LD11_SYS_CLK_AIO(idx) \
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UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 10), \
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UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2108, 0)
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@ -104,6 +112,7 @@ const struct uniphier_clk_data uniphier_pro4_sys_clk_data[] = {
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UNIPHIER_PRO4_SYS_CLK_GIO(12), /* Ether, SATA, USB3 */
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UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
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UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
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UNIPHIER_PRO4_SYS_CLK_AIO(40),
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{ /* sentinel */ }
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};
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@ -132,6 +141,7 @@ const struct uniphier_clk_data uniphier_pro5_sys_clk_data[] = {
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UNIPHIER_PRO4_SYS_CLK_GIO(12), /* PCIe, USB3 */
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UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
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UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
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UNIPHIER_PRO5_SYS_CLK_AIO(40),
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{ /* sentinel */ }
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};
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@ -149,6 +159,7 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
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/* The document mentions 0x2104 bit 18, but not functional */
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UNIPHIER_CLK_GATE("usb30-phy", 16, NULL, 0x2104, 19),
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UNIPHIER_CLK_GATE("usb31-phy", 20, NULL, 0x2104, 20),
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UNIPHIER_PRO5_SYS_CLK_AIO(40),
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{ /* sentinel */ }
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};
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