rtc: pcf2127: add support for PCF2131 RTC
This RTC is very similar in functionality to the PCF2127/29. Basically it: -supports two new control registers at offsets 4 and 5 -supports a new reset register (not implemented in this driver) -supports 4 tamper detection functions instead of 1 -has no nvmem (like the PCF2129) -has two output interrupt pins Because of that, most of the register addresses are very different, although they still follow the same layout. For example, the tamper registers have a different base address, but the offsets are all the same. Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com> Link: https://lore.kernel.org/r/20230622145800.2442116-12-hugo@hugovil.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
This commit is contained in:
Hugo Villeneuve
Alexandre Belloni
parent
420cc9e850
commit
afc505bf90
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@ -904,9 +904,9 @@ config RTC_DRV_PCF2127
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select REGMAP_SPI if SPI_MASTER
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select WATCHDOG_CORE if WATCHDOG
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help
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If you say yes here you get support for the NXP PCF2127/29 RTC
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If you say yes here you get support for the NXP PCF2127/29/31 RTC
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chips with integrated quartz crystal for industrial applications.
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Both chips also have watchdog timer and tamper switch detection
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These chips also have watchdog timer and tamper switch detection
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features.
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PCF2127 has an additional feature of 512 bytes battery backed
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* An I2C and SPI driver for the NXP PCF2127/29 RTC
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* An I2C and SPI driver for the NXP PCF2127/29/31 RTC
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* Copyright 2013 Til-Technologies
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*
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* Author: Renaud Cerrato <r.cerrato@til-technologies.fr>
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@ -8,9 +8,13 @@
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* Watchdog and tamper functions
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* Author: Bruno Thomsen <bruno.thomsen@gmail.com>
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*
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* PCF2131 support
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* Author: Hugo Villeneuve <hvilleneuve@dimonoff.com>
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*
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* based on the other drivers in this same directory.
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*
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* Datasheet: https://www.nxp.com/docs/en/data-sheet/PCF2127.pdf
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* Datasheets: https://www.nxp.com/docs/en/data-sheet/PCF2127.pdf
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* https://www.nxp.com/docs/en/data-sheet/PCF2131DS.pdf
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*/
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#include <linux/i2c.h>
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@ -67,7 +71,7 @@
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* RAM registers
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* PCF2127 has 512 bytes general-purpose static RAM (SRAM) that is
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* battery backed and can survive a power outage.
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* PCF2129 doesn't have this feature.
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* PCF2129/31 doesn't have this feature.
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*/
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#define PCF2127_REG_RAM_ADDR_MSB 0x1A
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#define PCF2127_REG_RAM_WRT_CMD 0x1C
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@ -86,11 +90,65 @@
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PCF2127_BIT_CTRL2_WDTF | \
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PCF2127_BIT_CTRL2_TSF2)
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#define PCF2127_MAX_TS_SUPPORTED 1
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#define PCF2127_MAX_TS_SUPPORTED 4
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/* Control register 4 */
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#define PCF2131_REG_CTRL4 0x03
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#define PCF2131_BIT_CTRL4_TSF4 BIT(4)
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#define PCF2131_BIT_CTRL4_TSF3 BIT(5)
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#define PCF2131_BIT_CTRL4_TSF2 BIT(6)
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#define PCF2131_BIT_CTRL4_TSF1 BIT(7)
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/* Control register 5 */
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#define PCF2131_REG_CTRL5 0x04
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#define PCF2131_BIT_CTRL5_TSIE4 BIT(4)
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#define PCF2131_BIT_CTRL5_TSIE3 BIT(5)
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#define PCF2131_BIT_CTRL5_TSIE2 BIT(6)
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#define PCF2131_BIT_CTRL5_TSIE1 BIT(7)
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/* Software reset register */
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#define PCF2131_REG_SR_RESET 0x05
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#define PCF2131_SR_RESET_READ_PATTERN (BIT(2) | BIT(5))
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#define PCF2131_SR_RESET_CPR_CMD (PCF2131_SR_RESET_READ_PATTERN | BIT(7))
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/* Time and date registers */
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#define PCF2131_REG_TIME_BASE 0x07
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/* Alarm registers */
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#define PCF2131_REG_ALARM_BASE 0x0E
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/* CLKOUT control register */
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#define PCF2131_REG_CLKOUT 0x13
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/* Watchdog registers */
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#define PCF2131_REG_WD_CTL 0x35
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#define PCF2131_REG_WD_VAL 0x36
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/* Tamper timestamp1 registers */
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#define PCF2131_REG_TS1_BASE 0x14
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/* Tamper timestamp2 registers */
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#define PCF2131_REG_TS2_BASE 0x1B
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/* Tamper timestamp3 registers */
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#define PCF2131_REG_TS3_BASE 0x22
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/* Tamper timestamp4 registers */
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#define PCF2131_REG_TS4_BASE 0x29
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/* Interrupt mask registers */
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#define PCF2131_REG_INT_A_MASK1 0x31
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#define PCF2131_REG_INT_A_MASK2 0x32
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#define PCF2131_REG_INT_B_MASK1 0x33
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#define PCF2131_REG_INT_B_MASK2 0x34
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#define PCF2131_BIT_INT_BLIE BIT(0)
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#define PCF2131_BIT_INT_BIE BIT(1)
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#define PCF2131_BIT_INT_AIE BIT(2)
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#define PCF2131_BIT_INT_WD_CD BIT(3)
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#define PCF2131_BIT_INT_SI BIT(4)
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#define PCF2131_BIT_INT_MI BIT(5)
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#define PCF2131_CTRL2_IRQ_MASK ( \
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PCF2127_BIT_CTRL2_AF | \
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PCF2127_BIT_CTRL2_WDTF)
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#define PCF2131_CTRL4_IRQ_MASK ( \
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PCF2131_BIT_CTRL4_TSF4 | \
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PCF2131_BIT_CTRL4_TSF3 | \
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PCF2131_BIT_CTRL4_TSF2 | \
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PCF2131_BIT_CTRL4_TSF1)
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enum pcf21xx_type {
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PCF2127,
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PCF2129,
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PCF2131,
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PCF21XX_LAST_ID
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};
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@ -530,30 +588,64 @@ static void pcf2127_rtc_ts_snapshot(struct device *dev, int ts_id)
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static irqreturn_t pcf2127_rtc_irq(int irq, void *dev)
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{
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struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
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unsigned int ctrl1, ctrl2;
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unsigned int ctrl2;
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int ret = 0;
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ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1);
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if (ret)
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return IRQ_NONE;
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ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2);
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if (ret)
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return IRQ_NONE;
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if (!(ctrl1 & PCF2127_CTRL1_IRQ_MASK || ctrl2 & PCF2127_CTRL2_IRQ_MASK))
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return IRQ_NONE;
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if (pcf2127->cfg->ts_count == 1) {
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/* PCF2127/29 */
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unsigned int ctrl1;
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if (ctrl1 & PCF2127_BIT_CTRL1_TSF1 || ctrl2 & PCF2127_BIT_CTRL2_TSF2)
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pcf2127_rtc_ts_snapshot(dev, 0);
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ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1);
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if (ret)
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return IRQ_NONE;
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if (ctrl1 & PCF2127_CTRL1_IRQ_MASK)
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regmap_write(pcf2127->regmap, PCF2127_REG_CTRL1,
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ctrl1 & ~PCF2127_CTRL1_IRQ_MASK);
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if (!(ctrl1 & PCF2127_CTRL1_IRQ_MASK || ctrl2 & PCF2127_CTRL2_IRQ_MASK))
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return IRQ_NONE;
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if (ctrl2 & PCF2127_CTRL2_IRQ_MASK)
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regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2,
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ctrl2 & ~PCF2127_CTRL2_IRQ_MASK);
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if (ctrl1 & PCF2127_BIT_CTRL1_TSF1 || ctrl2 & PCF2127_BIT_CTRL2_TSF2)
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pcf2127_rtc_ts_snapshot(dev, 0);
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if (ctrl1 & PCF2127_CTRL1_IRQ_MASK)
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regmap_write(pcf2127->regmap, PCF2127_REG_CTRL1,
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ctrl1 & ~PCF2127_CTRL1_IRQ_MASK);
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if (ctrl2 & PCF2127_CTRL2_IRQ_MASK)
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regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2,
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ctrl2 & ~PCF2127_CTRL2_IRQ_MASK);
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} else {
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/* PCF2131. */
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unsigned int ctrl4;
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ret = regmap_read(pcf2127->regmap, PCF2131_REG_CTRL4, &ctrl4);
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if (ret)
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return IRQ_NONE;
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if (!(ctrl4 & PCF2131_CTRL4_IRQ_MASK || ctrl2 & PCF2131_CTRL2_IRQ_MASK))
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return IRQ_NONE;
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if (ctrl4 & PCF2131_CTRL4_IRQ_MASK) {
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int i;
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int tsf_bit = PCF2131_BIT_CTRL4_TSF1; /* Start at bit 7. */
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for (i = 0; i < pcf2127->cfg->ts_count; i++) {
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if (ctrl4 & tsf_bit)
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pcf2127_rtc_ts_snapshot(dev, i);
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tsf_bit = tsf_bit >> 1;
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}
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regmap_write(pcf2127->regmap, PCF2131_REG_CTRL4,
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ctrl4 & ~PCF2131_CTRL4_IRQ_MASK);
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}
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if (ctrl2 & PCF2131_CTRL2_IRQ_MASK)
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regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2,
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ctrl2 & ~PCF2131_CTRL2_IRQ_MASK);
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}
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if (ctrl2 & PCF2127_BIT_CTRL2_AF)
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rtc_update_irq(pcf2127->rtc, 1, RTC_IRQF | RTC_AF);
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@ -626,6 +718,27 @@ static ssize_t timestamp0_store(struct device *dev,
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return timestamp_store(dev, attr, buf, count, 0);
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};
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static ssize_t timestamp1_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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return timestamp_store(dev, attr, buf, count, 1);
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};
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static ssize_t timestamp2_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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return timestamp_store(dev, attr, buf, count, 2);
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};
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static ssize_t timestamp3_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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return timestamp_store(dev, attr, buf, count, 3);
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};
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static ssize_t timestamp_show(struct device *dev,
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struct device_attribute *attr, char *buf,
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int ts_id)
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@ -690,13 +803,42 @@ static ssize_t timestamp0_show(struct device *dev,
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return timestamp_show(dev, attr, buf, 0);
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};
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static ssize_t timestamp1_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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return timestamp_show(dev, attr, buf, 1);
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};
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static ssize_t timestamp2_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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return timestamp_show(dev, attr, buf, 2);
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};
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static ssize_t timestamp3_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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return timestamp_show(dev, attr, buf, 3);
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};
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static DEVICE_ATTR_RW(timestamp0);
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static DEVICE_ATTR_RW(timestamp1);
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static DEVICE_ATTR_RW(timestamp2);
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static DEVICE_ATTR_RW(timestamp3);
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static struct attribute *pcf2127_attrs[] = {
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&dev_attr_timestamp0.attr,
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NULL
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};
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static struct attribute *pcf2131_attrs[] = {
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&dev_attr_timestamp0.attr,
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&dev_attr_timestamp1.attr,
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&dev_attr_timestamp2.attr,
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&dev_attr_timestamp3.attr,
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NULL
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};
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static struct pcf21xx_config pcf21xx_cfg[] = {
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[PCF2127] = {
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.type = PCF2127,
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@ -746,6 +888,53 @@ static struct pcf21xx_config pcf21xx_cfg[] = {
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.attrs = pcf2127_attrs,
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},
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},
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[PCF2131] = {
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.type = PCF2131,
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.max_register = 0x36,
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.has_nvmem = 0,
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.has_bit_wd_ctl_cd0 = 0,
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.reg_time_base = PCF2131_REG_TIME_BASE,
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.regs_alarm_base = PCF2131_REG_ALARM_BASE,
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.reg_wd_ctl = PCF2131_REG_WD_CTL,
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.reg_wd_val = PCF2131_REG_WD_VAL,
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.reg_clkout = PCF2131_REG_CLKOUT,
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.ts_count = 4,
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.ts[0] = {
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.reg_base = PCF2131_REG_TS1_BASE,
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.gnd_detect_reg = PCF2131_REG_CTRL4,
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.gnd_detect_bit = PCF2131_BIT_CTRL4_TSF1,
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.inter_detect_bit = 0,
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.ie_reg = PCF2131_REG_CTRL5,
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.ie_bit = PCF2131_BIT_CTRL5_TSIE1,
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},
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.ts[1] = {
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.reg_base = PCF2131_REG_TS2_BASE,
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.gnd_detect_reg = PCF2131_REG_CTRL4,
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.gnd_detect_bit = PCF2131_BIT_CTRL4_TSF2,
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.inter_detect_bit = 0,
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.ie_reg = PCF2131_REG_CTRL5,
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.ie_bit = PCF2131_BIT_CTRL5_TSIE2,
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},
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.ts[2] = {
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.reg_base = PCF2131_REG_TS3_BASE,
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.gnd_detect_reg = PCF2131_REG_CTRL4,
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.gnd_detect_bit = PCF2131_BIT_CTRL4_TSF3,
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.inter_detect_bit = 0,
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.ie_reg = PCF2131_REG_CTRL5,
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.ie_bit = PCF2131_BIT_CTRL5_TSIE3,
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},
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.ts[3] = {
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.reg_base = PCF2131_REG_TS4_BASE,
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.gnd_detect_reg = PCF2131_REG_CTRL4,
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.gnd_detect_bit = PCF2131_BIT_CTRL4_TSF4,
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.inter_detect_bit = 0,
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.ie_reg = PCF2131_REG_CTRL5,
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.ie_bit = PCF2131_BIT_CTRL5_TSIE4,
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},
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.attribute_group = {
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.attrs = pcf2131_attrs,
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},
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},
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};
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/*
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@ -893,7 +1082,7 @@ static int pcf2127_probe(struct device *dev, struct regmap *regmap,
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* Watchdog timer enabled and reset pin /RST activated when timed out.
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* Select 1Hz clock source for watchdog timer.
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* Note: Countdown timer disabled and not available.
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* For pca2129, pcf2129, only bit[7] is for Symbol WD_CD
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* For pca2129, pcf2129 and pcf2131, only bit[7] is for Symbol WD_CD
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* of register watchdg_tim_ctl. The bit[6] is labeled
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* as T. Bits labeled as T must always be written with
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* logic 0.
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@ -953,6 +1142,7 @@ static const struct of_device_id pcf2127_of_match[] = {
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{ .compatible = "nxp,pcf2127", .data = &pcf21xx_cfg[PCF2127] },
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{ .compatible = "nxp,pcf2129", .data = &pcf21xx_cfg[PCF2129] },
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{ .compatible = "nxp,pca2129", .data = &pcf21xx_cfg[PCF2129] },
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{ .compatible = "nxp,pcf2131", .data = &pcf21xx_cfg[PCF2131] },
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{}
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};
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MODULE_DEVICE_TABLE(of, pcf2127_of_match);
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@ -1040,6 +1230,7 @@ static const struct i2c_device_id pcf2127_i2c_id[] = {
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{ "pcf2127", PCF2127 },
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{ "pcf2129", PCF2129 },
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{ "pca2129", PCF2129 },
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{ "pcf2131", PCF2131 },
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{ }
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};
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MODULE_DEVICE_TABLE(i2c, pcf2127_i2c_id);
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@ -1161,6 +1352,7 @@ static const struct spi_device_id pcf2127_spi_id[] = {
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{ "pcf2127", PCF2127 },
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{ "pcf2129", PCF2129 },
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{ "pca2129", PCF2129 },
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{ "pcf2131", PCF2131 },
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{ }
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};
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MODULE_DEVICE_TABLE(spi, pcf2127_spi_id);
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@ -1225,5 +1417,5 @@ static void __exit pcf2127_exit(void)
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module_exit(pcf2127_exit)
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MODULE_AUTHOR("Renaud Cerrato <r.cerrato@til-technologies.fr>");
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MODULE_DESCRIPTION("NXP PCF2127/29 RTC driver");
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MODULE_DESCRIPTION("NXP PCF2127/29/31 RTC driver");
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MODULE_LICENSE("GPL v2");
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