[PATCH] ARM: 2797/1: OMAP update 1/11: Update include files
Patch from Tony Lindgren This patch by various OMAP developers syncs the OMAP specific include files with the linux-omap tree. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Tony Lindgren
Russell King
parent
8107338bf9
commit
af973d2aff
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@ -34,11 +34,6 @@
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/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
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#define OMAP1610_ETHR_START 0x04000300
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/* Intel STRATA NOR flash at CS3 or CS2B(NAND Boot) */
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#define OMAP_NOR_FLASH_SIZE SZ_32M
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#define OMAP_NOR_FLASH_START1 0x0C000000 /* CS3 */
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#define OMAP_NOR_FLASH_START2 0x0A000000 /* CS2B */
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/* Samsung NAND flash at CS2B or CS3(NAND Boot) */
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#define OMAP_NAND_FLASH_START1 0x0A000000 /* CS2B */
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#define OMAP_NAND_FLASH_START2 0x0C000000 /* CS3 */
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@ -30,11 +30,6 @@
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/* In OMAP1710 H3 the Ethernet is directly connected to CS1 */
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#define OMAP1710_ETHR_START 0x04000300
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/* Intel STRATA NOR flash at CS3 or CS2B(NAND Boot) */
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#define OMAP_NOR_FLASH_SIZE SZ_32M
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#define OMAP_NOR_FLASH_START1 0x0C000000 /* CS3 */
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#define OMAP_NOR_FLASH_START2 0x0A000000 /* CS2B */
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/* Samsung NAND flash at CS2B or CS3(NAND Boot) */
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#define OMAP_NAND_FLASH_START1 0x0A000000 /* CS2B */
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#define OMAP_NAND_FLASH_START2 0x0C000000 /* CS3 */
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@ -32,10 +32,5 @@
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/* At OMAP5912 OSK the Ethernet is directly connected to CS1 */
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#define OMAP_OSK_ETHR_START 0x04800300
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/* Micron NOR flash at CS3 mapped to address 0x0 if BM bit is 1 */
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#define OMAP_OSK_NOR_FLASH_BASE 0xD8000000
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#define OMAP_OSK_NOR_FLASH_SIZE SZ_32M
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#define OMAP_OSK_NOR_FLASH_START 0x00000000
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#endif /* __ASM_ARCH_OMAP_OSK_H */
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@ -16,10 +16,11 @@
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/* Different peripheral ids */
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#define OMAP_TAG_CLOCK 0x4f01
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#define OMAP_TAG_MMC 0x4f02
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#define OMAP_TAG_UART 0x4f03
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#define OMAP_TAG_SERIAL_CONSOLE 0x4f03
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#define OMAP_TAG_USB 0x4f04
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#define OMAP_TAG_LCD 0x4f05
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#define OMAP_TAG_GPIO_SWITCH 0x4f06
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#define OMAP_TAG_UART 0x4f07
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#define OMAP_TAG_BOOT_REASON 0x4f80
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#define OMAP_TAG_FLASH_PART 0x4f81
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@ -35,7 +36,7 @@ struct omap_mmc_config {
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s16 mmc1_switch_pin, mmc2_switch_pin;
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};
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struct omap_uart_config {
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struct omap_serial_console_config {
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u8 console_uart;
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u32 console_speed;
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};
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@ -82,7 +83,8 @@ struct omap_lcd_config {
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*/
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#define OMAP_GPIO_SWITCH_TYPE_COVER 0x0000
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#define OMAP_GPIO_SWITCH_TYPE_CONNECTION 0x0001
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#define OMAP_GPIO_SWITCH_FLAG_INVERTED 0x0001
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#define OMAP_GPIO_SWITCH_FLAG_INVERTED 0x0001
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#define OMAP_GPIO_SWITCH_FLAG_OUTPUT 0x0002
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struct omap_gpio_switch_config {
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char name[12];
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u16 gpio;
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@ -99,6 +101,10 @@ struct omap_boot_reason_config {
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char reason_str[12];
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};
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struct omap_uart_config {
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/* Bit field of UARTs present; bit 0 --> UART1 */
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unsigned int enabled_uarts;
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};
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struct omap_board_config_entry {
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u16 tag;
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@ -52,6 +52,19 @@
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* ---------------------------------------------------------------------------
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*/
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/*
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* ----------------------------------------------------------------------------
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* Timers
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* ----------------------------------------------------------------------------
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*/
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#define OMAP_MPU_TIMER1_BASE (0xfffec500)
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#define OMAP_MPU_TIMER2_BASE (0xfffec600)
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#define OMAP_MPU_TIMER3_BASE (0xfffec700)
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#define MPU_TIMER_FREE (1 << 6)
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#define MPU_TIMER_CLOCK_ENABLE (1 << 5)
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#define MPU_TIMER_AR (1 << 1)
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#define MPU_TIMER_ST (1 << 0)
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/*
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* ----------------------------------------------------------------------------
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* Clocks
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@ -78,6 +91,7 @@
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/* DSP clock control */
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#define DSP_CONFIG_REG_BASE (0xe1008000)
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#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)
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#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
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#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
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@ -88,6 +102,7 @@
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*/
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#define ULPD_REG_BASE (0xfffe0800)
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#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14)
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#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24)
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#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)
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# define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */
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# define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */
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@ -268,17 +283,10 @@
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* Processor specific defines
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* ---------------------------------------------------------------------------
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*/
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#ifdef CONFIG_ARCH_OMAP730
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#include "omap730.h"
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#endif
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#ifdef CONFIG_ARCH_OMAP1510
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#include "omap1510.h"
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#endif
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#ifdef CONFIG_ARCH_OMAP16XX
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#include "omap16xx.h"
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#endif
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/*
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* ---------------------------------------------------------------------------
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@ -159,6 +159,7 @@
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#define INT_1610_GPIO_BANK3 (41 + IH2_BASE)
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#define INT_1610_MMC2 (42 + IH2_BASE)
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#define INT_1610_CF (43 + IH2_BASE)
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#define INT_1610_WAKE_UP_REQ (46 + IH2_BASE)
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#define INT_1610_GPIO_BANK4 (48 + IH2_BASE)
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#define INT_1610_SPI (49 + IH2_BASE)
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#define INT_1610_DMA_CH6 (53 + IH2_BASE)
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@ -238,6 +239,8 @@
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#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
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#define IH_BOARD_BASE (16 + IH_MPUIO_BASE)
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#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
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#ifndef __ASSEMBLY__
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extern void omap_init_irq(void);
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#endif
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@ -183,5 +183,37 @@
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#define OMAP16XX_PWL_ENABLE (OMAP16XX_PWL_BASE + 0x00)
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#define OMAP16XX_PWL_CLK_ENABLE (OMAP16XX_PWL_BASE + 0x04)
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/*
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* ---------------------------------------------------------------------------
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* Watchdog timer
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* ---------------------------------------------------------------------------
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*/
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/* 32-bit Watchdog timer in OMAP 16XX */
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#define OMAP_16XX_WATCHDOG_BASE (0xfffeb000)
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#define OMAP_16XX_WIDR (OMAP_16XX_WATCHDOG_BASE + 0x00)
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#define OMAP_16XX_WD_SYSCONFIG (OMAP_16XX_WATCHDOG_BASE + 0x10)
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#define OMAP_16XX_WD_SYSSTATUS (OMAP_16XX_WATCHDOG_BASE + 0x14)
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#define OMAP_16XX_WCLR (OMAP_16XX_WATCHDOG_BASE + 0x24)
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#define OMAP_16XX_WCRR (OMAP_16XX_WATCHDOG_BASE + 0x28)
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#define OMAP_16XX_WLDR (OMAP_16XX_WATCHDOG_BASE + 0x2c)
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#define OMAP_16XX_WTGR (OMAP_16XX_WATCHDOG_BASE + 0x30)
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#define OMAP_16XX_WWPS (OMAP_16XX_WATCHDOG_BASE + 0x34)
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#define OMAP_16XX_WSPR (OMAP_16XX_WATCHDOG_BASE + 0x48)
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#define WCLR_PRE_SHIFT 5
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#define WCLR_PTV_SHIFT 2
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#define WWPS_W_PEND_WSPR (1 << 4)
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#define WWPS_W_PEND_WTGR (1 << 3)
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#define WWPS_W_PEND_WLDR (1 << 2)
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#define WWPS_W_PEND_WCRR (1 << 1)
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#define WWPS_W_PEND_WCLR (1 << 0)
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#define WSPR_ENABLE_0 (0x0000bbbb)
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#define WSPR_ENABLE_1 (0x00004444)
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#define WSPR_DISABLE_0 (0x0000aaaa)
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#define WSPR_DISABLE_1 (0x00005555)
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#endif /* __ASM_ARCH_OMAP16XX_H */
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@ -5,7 +5,9 @@
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#ifndef __ASM_ARCH_SYSTEM_H
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#define __ASM_ARCH_SYSTEM_H
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#include <linux/config.h>
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#include <asm/mach-types.h>
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#include <asm/arch/hardware.h>
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#include <asm/mach-types.h>
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static inline void arch_idle(void)
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{
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@ -14,7 +16,24 @@ static inline void arch_idle(void)
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static inline void arch_reset(char mode)
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{
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omap_writew(1, ARM_RSTCT1);
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#ifdef CONFIG_ARCH_OMAP16XX
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/*
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* Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
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* "Global Software Reset Affects Traffic Controller Frequency".
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*/
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if (cpu_is_omap5912()) {
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omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4),
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DPLL_CTL);
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omap_writew(0x8, ARM_RSTCT1);
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}
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#endif
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#ifdef CONFIG_MACH_VOICEBLUE
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if (machine_is_voiceblue())
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voiceblue_reset();
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else
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#endif
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omap_writew(1, ARM_RSTCT1);
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}
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#endif
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