pci-v6.6-fixes-2
-----BEGIN PGP SIGNATURE----- iQJIBAABCgAyFiEEgMe7l+5h9hnxdsnuWYigwDrT+vwFAmUgHWsUHGJoZWxnYWFz QGdvb2dsZS5jb20ACgkQWYigwDrT+vxMJg//T5TAOGAChU8YoPoUMsVeRYNOqkG9 G+rWydRr/Mj7dWg0zdi5L7fi/krFx+BdSpaq4DnVu6YgGboLnlP+Z4/gqXeFfO+j lPP5OG3uOOLkw7aktYCRFdSkryrzm02eQDfiT/boL9hqF1ioyoWHgk4E7AITYgkH /ZHL/R6OllwuLfqI9MAFZ/9aKkTtezSqTGOMnOZSUu/OykP26hJhCmq4SlmZoVwV lc6DdxCzACfgnX1dOiaia42PaDbU0niwtiQw56bksk1oebEULbr/OuKRRm5zjfTE 5aLXJbrM5W8KOnO6sTuDy2FDb/BlFi3dC+TF1FrAEqnnuY3nHDSpNSiAmu3JU4qA pHMLRoVWcewoDlI4cqeTg2eh8n82pnfkl8UOtgi0KzmCnaZzoZzr3aYQ9etK7XcK CGFmGaoQ9zXXH60VCiRqSTcr11PoVulIbn+Aa6s3uw5KQxvDArPLuMl1ljngCinR U127D77u//BqjRVdB9mY69JCXyp9LCwBJ/tN20Jj1yeDfX43OgB0oSy7A7eYQwoZ oydgSaSE0bRSEl6lRmmQsNhz3Qcwe/l+x+LNEpU2IBMkUD4SuW5L2zjZAmzHtM/6 9mUBLUh9JhxTk+2/7q0DL4UiMmx2AKkdt5vCNdDeFmKF+MYg7YYEfORRJYlSTDcO Ay6aBBcoV4KXGnk= =6O20 -----END PGP SIGNATURE----- Merge tag 'pci-v6.6-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci Pull PCI fixes from Bjorn Helgaas: - Fix a qcom register offset that broke IPQ8074 PCIe controller enumeration (Sricharan Ramabadhran) - Handle interrupt parsing failures when creating a device tree node to avoid using uninitialized data (Lizhi Hou) - Clean up if adding PCI device node fails when creating a device tree node to avoid a memory leak (Lizhi Hou) - If a link is down, mark all downstream devices as "disconnected" so we don't wait for them on resume (Mika Westerberg) * tag 'pci-v6.6-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: PCI/PM: Mark devices disconnected if upstream PCIe link is down on resume PCI: of: Destroy changeset when adding PCI device node fails PCI: of_property: Handle interrupt parsing failures PCI: qcom: Fix IPQ8074 enumeration
This commit is contained in:
commit
af95dc6fdc
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@ -43,7 +43,6 @@
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#define PARF_PHY_REFCLK 0x4c
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#define PARF_CONFIG_BITS 0x50
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#define PARF_DBI_BASE_ADDR 0x168
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#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x16c /* Register offset specific to IP ver 2.3.3 */
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#define PARF_MHI_CLOCK_RESET_CTRL 0x174
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#define PARF_AXI_MSTR_WR_ADDR_HALT 0x178
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#define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8
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@ -797,8 +796,7 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie)
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u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
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u32 val;
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writel(SLV_ADDR_SPACE_SZ,
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pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_2_3_3);
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writel(SLV_ADDR_SPACE_SZ, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE);
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val = readl(pcie->parf + PARF_PHY_CTRL);
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val &= ~PHY_TEST_PWR_DOWN;
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@ -657,30 +657,33 @@ void of_pci_make_dev_node(struct pci_dev *pdev)
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cset = kmalloc(sizeof(*cset), GFP_KERNEL);
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if (!cset)
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goto failed;
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goto out_free_name;
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of_changeset_init(cset);
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np = of_changeset_create_node(cset, ppnode, name);
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if (!np)
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goto failed;
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np->data = cset;
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goto out_destroy_cset;
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ret = of_pci_add_properties(pdev, cset, np);
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if (ret)
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goto failed;
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goto out_free_node;
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ret = of_changeset_apply(cset);
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if (ret)
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goto failed;
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goto out_free_node;
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np->data = cset;
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pdev->dev.of_node = np;
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kfree(name);
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return;
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failed:
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if (np)
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of_node_put(np);
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out_free_node:
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of_node_put(np);
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out_destroy_cset:
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of_changeset_destroy(cset);
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kfree(cset);
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out_free_name:
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kfree(name);
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}
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#endif
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@ -186,8 +186,8 @@ static int of_pci_prop_interrupts(struct pci_dev *pdev,
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static int of_pci_prop_intr_map(struct pci_dev *pdev, struct of_changeset *ocs,
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struct device_node *np)
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{
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u32 i, addr_sz[OF_PCI_MAX_INT_PIN] = { 0 }, map_sz = 0;
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struct of_phandle_args out_irq[OF_PCI_MAX_INT_PIN];
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u32 i, addr_sz[OF_PCI_MAX_INT_PIN], map_sz = 0;
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__be32 laddr[OF_PCI_ADDRESS_CELLS] = { 0 };
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u32 int_map_mask[] = { 0xffff00, 0, 0, 7 };
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struct device_node *pnode;
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@ -213,33 +213,44 @@ static int of_pci_prop_intr_map(struct pci_dev *pdev, struct of_changeset *ocs,
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out_irq[i].args[0] = pin;
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ret = of_irq_parse_raw(laddr, &out_irq[i]);
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if (ret) {
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pci_err(pdev, "parse irq %d failed, ret %d", pin, ret);
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out_irq[i].np = NULL;
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pci_dbg(pdev, "parse irq %d failed, ret %d", pin, ret);
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continue;
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}
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ret = of_property_read_u32(out_irq[i].np, "#address-cells",
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&addr_sz[i]);
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if (ret)
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addr_sz[i] = 0;
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of_property_read_u32(out_irq[i].np, "#address-cells",
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&addr_sz[i]);
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}
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list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
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for (pin = 1; pin <= OF_PCI_MAX_INT_PIN; pin++) {
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i = pci_swizzle_interrupt_pin(child, pin) - 1;
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if (!out_irq[i].np)
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continue;
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map_sz += 5 + addr_sz[i] + out_irq[i].args_count;
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}
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}
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/*
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* Parsing interrupt failed for all pins. In this case, it does not
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* need to generate interrupt-map property.
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*/
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if (!map_sz)
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return 0;
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int_map = kcalloc(map_sz, sizeof(u32), GFP_KERNEL);
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mapp = int_map;
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list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
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for (pin = 1; pin <= OF_PCI_MAX_INT_PIN; pin++) {
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i = pci_swizzle_interrupt_pin(child, pin) - 1;
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if (!out_irq[i].np)
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continue;
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*mapp = (child->bus->number << 16) |
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(child->devfn << 8);
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mapp += OF_PCI_ADDRESS_CELLS;
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*mapp = pin;
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mapp++;
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i = pci_swizzle_interrupt_pin(child, pin) - 1;
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*mapp = out_irq[i].np->phandle;
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mapp++;
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if (addr_sz[i]) {
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@ -572,7 +572,19 @@ static void pci_pm_default_resume_early(struct pci_dev *pci_dev)
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static void pci_pm_bridge_power_up_actions(struct pci_dev *pci_dev)
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{
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pci_bridge_wait_for_secondary_bus(pci_dev, "resume");
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int ret;
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ret = pci_bridge_wait_for_secondary_bus(pci_dev, "resume");
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if (ret) {
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/*
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* The downstream link failed to come up, so mark the
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* devices below as disconnected to make sure we don't
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* attempt to resume them.
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*/
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pci_walk_bus(pci_dev->subordinate, pci_dev_set_disconnected,
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NULL);
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return;
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}
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/*
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* When powering on a bridge from D3cold, the whole hierarchy may be
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