UbiquitousOS
/
OpenCloudOS-Kernel
mirror of https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel.git
11
0
Fork 0
Code Issues Projects Releases Wiki Activity

phy: qcom-qmp-pcie: split pcs_misc region for ipq6018 pcie gen3 

Follow the example of other PCIe PHYs and use separate pcs_misc region
to access PCS_PCIE_* resources.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220705094320.1313312-5-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Dmitry Baryshkov 2022-07-05 12:42:56 +03:00 committed by Vinod Koul
parent fc64623637
commit af6643242d
2 changed files with 25 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
View File

@ -361,6 +361,9 @@ static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
};
static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = {
QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
@ -1593,6 +1596,8 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
.rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
.pcs_tbl = ipq6018_pcie_pcs_tbl,
.pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
.pcs_misc_tbl = ipq6018_pcie_pcs_misc_tbl,
.pcs_misc_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl),
.clk_list = ipq8074_pciephy_clk_l,
.num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
.reset_list = ipq8074_pciephy_reset_l,
@ -2374,6 +2379,10 @@ int qcom_qmp_phy_pcie_create(struct device *dev, struct device_node *np, int id,
qphy->pcs_misc = of_iomap(np, 3);
}
if (!qphy->pcs_misc &&
of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy"))
qphy->pcs_misc = qphy->pcs + 0x400;
if (!qphy->pcs_misc)
dev_vdbg(dev, "PHY pcs_misc-reg not used\n");

32
drivers/phy/qualcomm/phy-qcom-qmp.h
View File

@ -121,22 +121,22 @@
/* QMP V2 PHY for PCIE gen3 ports - PCS Misc registers */
#define PCS_PCIE_POWER_STATE_CONFIG2 0x40c
#define PCS_PCIE_POWER_STATE_CONFIG4 0x414
#define PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x41c
#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x440
#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x444
#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x448
#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x44c
#define PCS_PCIE_OSC_DTCT_CONFIG2 0x45c
#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x478
#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x480
#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x484
#define PCS_PCIE_OSC_DTCT_ACTIONS 0x490
#define PCS_PCIE_EQ_CONFIG1 0x4a0
#define PCS_PCIE_EQ_CONFIG2 0x4a4
#define PCS_PCIE_PRESET_P10_PRE 0x4bc
#define PCS_PCIE_PRESET_P10_POST 0x4e0
#define PCS_PCIE_POWER_STATE_CONFIG2 0x00c
#define PCS_PCIE_POWER_STATE_CONFIG4 0x014
#define PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x040
#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x044
#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x048
#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x04c
#define PCS_PCIE_OSC_DTCT_CONFIG2 0x05c
#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x078
#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x080
#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x084
#define PCS_PCIE_OSC_DTCT_ACTIONS 0x090
#define PCS_PCIE_EQ_CONFIG1 0x0a0
#define PCS_PCIE_EQ_CONFIG2 0x0a4
#define PCS_PCIE_PRESET_P10_PRE 0x0bc
#define PCS_PCIE_PRESET_P10_POST 0x0e0
/* Only for QMP V2 PHY - QSERDES COM registers */
#define QSERDES_COM_BG_TIMER 0x00c