Merge branch 'remotes/lorenzo/pci/al'
- Add driver for Amazon Annapurna Labs PCIe controller (Jonathan Chocron)
- Disable MSI-X since Annapurna Labs advertises it, but it's broken
(Jonathan Chocron)
- Disable VPD since Annapurna Labs advertises it, but it's broken
(Jonathan Chocron)
- Add ACS quirk since Annapurna Labs doesn't support ACS but does provide
some equivalent protections (Ali Saidi)
* remotes/lorenzo/pci/al:
PCI: dwc: Add validation that PCIe core is set to correct mode
PCI: dwc: al: Add Amazon Annapurna Labs PCIe controller driver
dt-bindings: PCI: Add Amazon's Annapurna Labs PCIe host bridge binding
PCI: Add quirk to disable MSI-X support for Amazon's Annapurna Labs Root Port
PCI/VPD: Prevent VPD access for Amazon's Annapurna Labs Root Port
PCI: Add ACS quirk for Amazon Annapurna Labs root ports
PCI: Add Amazon's Annapurna Labs vendor ID
# Conflicts:
# drivers/pci/quirks.c
This commit is contained in:
Bjorn Helgaas
commit
af47f25f33
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|
@ -0,0 +1,46 @@
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* Amazon Annapurna Labs PCIe host bridge
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Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys DesignWare
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PCI core. It inherits common properties defined in
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Documentation/devicetree/bindings/pci/designware-pcie.txt.
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Properties of the host controller node that differ from it are:
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- compatible:
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Usage: required
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Value type: <stringlist>
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Definition: Value should contain
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- "amazon,al-alpine-v2-pcie" for alpine_v2
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- "amazon,al-alpine-v3-pcie" for alpine_v3
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- reg:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: Register ranges as listed in the reg-names property
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- reg-names:
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Usage: required
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Value type: <stringlist>
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Definition: Must include the following entries
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- "config" PCIe ECAM space
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- "controller" AL proprietary registers
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- "dbi" Designware PCIe registers
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Example:
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pcie-external0: pcie@fb600000 {
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compatible = "amazon,al-alpine-v3-pcie";
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reg = <0x0 0xfb600000 0x0 0x00100000
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0x0 0xfd800000 0x0 0x00010000
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0x0 0xfd810000 0x0 0x00001000>;
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reg-names = "config", "controller", "dbi";
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bus-range = <0 255>;
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-map-mask = <0x00 0 0 7>;
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interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; /* INTa */
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ranges = <0x02000000 0x0 0xc0010000 0x0 0xc0010000 0x0 0x07ff0000>;
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};
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@ -12448,10 +12448,11 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/pci.git/
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S: Supported
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F: drivers/pci/controller/
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PCIE DRIVER FOR ANNAPURNA LABS
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PCIE DRIVER FOR AMAZON ANNAPURNA LABS
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M: Jonathan Chocron <jonnyc@amazon.com>
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L: linux-pci@vger.kernel.org
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S: Maintained
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F: Documentation/devicetree/bindings/pci/pcie-al.txt
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F: drivers/pci/controller/dwc/pcie-al.c
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PCIE DRIVER FOR AMLOGIC MESON
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|
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@ -230,4 +230,16 @@ config PCIE_UNIPHIER
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Say Y here if you want PCIe controller support on UniPhier SoCs.
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This driver supports LD20 and PXs3 SoCs.
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config PCIE_AL
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bool "Amazon Annapurna Labs PCIe controller"
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depends on OF && (ARM64 || COMPILE_TEST)
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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help
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Say Y here to enable support of the Amazon's Annapurna Labs PCIe
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controller IP on Amazon SoCs. The PCIe controller uses the DesignWare
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core plus Annapurna Labs proprietary hardware wrappers. This is
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required only for DT-based platforms. ACPI platforms with the
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Annapurna Labs PCIe controller don't need to enable this.
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endmenu
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|
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@ -91,3 +91,368 @@ struct pci_ecam_ops al_pcie_ops = {
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};
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#endif /* defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS) */
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#ifdef CONFIG_PCIE_AL
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#include <linux/of_pci.h>
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#include "pcie-designware.h"
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#define AL_PCIE_REV_ID_2 2
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#define AL_PCIE_REV_ID_3 3
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#define AL_PCIE_REV_ID_4 4
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#define AXI_BASE_OFFSET 0x0
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#define DEVICE_ID_OFFSET 0x16c
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#define DEVICE_REV_ID 0x0
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#define DEVICE_REV_ID_DEV_ID_MASK GENMASK(31, 16)
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#define DEVICE_REV_ID_DEV_ID_X4 0
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#define DEVICE_REV_ID_DEV_ID_X8 2
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#define DEVICE_REV_ID_DEV_ID_X16 4
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#define OB_CTRL_REV1_2_OFFSET 0x0040
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#define OB_CTRL_REV3_5_OFFSET 0x0030
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#define CFG_TARGET_BUS 0x0
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#define CFG_TARGET_BUS_MASK_MASK GENMASK(7, 0)
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#define CFG_TARGET_BUS_BUSNUM_MASK GENMASK(15, 8)
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#define CFG_CONTROL 0x4
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#define CFG_CONTROL_SUBBUS_MASK GENMASK(15, 8)
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#define CFG_CONTROL_SEC_BUS_MASK GENMASK(23, 16)
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struct al_pcie_reg_offsets {
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unsigned int ob_ctrl;
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};
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struct al_pcie_target_bus_cfg {
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u8 reg_val;
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u8 reg_mask;
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u8 ecam_mask;
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};
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struct al_pcie {
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struct dw_pcie *pci;
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void __iomem *controller_base; /* base of PCIe unit (not DW core) */
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struct device *dev;
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resource_size_t ecam_size;
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unsigned int controller_rev_id;
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struct al_pcie_reg_offsets reg_offsets;
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struct al_pcie_target_bus_cfg target_bus_cfg;
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};
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#define PCIE_ECAM_DEVFN(x) (((x) & 0xff) << 12)
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#define to_al_pcie(x) dev_get_drvdata((x)->dev)
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static inline u32 al_pcie_controller_readl(struct al_pcie *pcie, u32 offset)
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{
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return readl_relaxed(pcie->controller_base + offset);
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}
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static inline void al_pcie_controller_writel(struct al_pcie *pcie, u32 offset,
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u32 val)
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{
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writel_relaxed(val, pcie->controller_base + offset);
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}
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static int al_pcie_rev_id_get(struct al_pcie *pcie, unsigned int *rev_id)
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{
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u32 dev_rev_id_val;
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u32 dev_id_val;
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dev_rev_id_val = al_pcie_controller_readl(pcie, AXI_BASE_OFFSET +
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DEVICE_ID_OFFSET +
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DEVICE_REV_ID);
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dev_id_val = FIELD_GET(DEVICE_REV_ID_DEV_ID_MASK, dev_rev_id_val);
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switch (dev_id_val) {
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case DEVICE_REV_ID_DEV_ID_X4:
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*rev_id = AL_PCIE_REV_ID_2;
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break;
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case DEVICE_REV_ID_DEV_ID_X8:
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*rev_id = AL_PCIE_REV_ID_3;
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break;
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case DEVICE_REV_ID_DEV_ID_X16:
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*rev_id = AL_PCIE_REV_ID_4;
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break;
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default:
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dev_err(pcie->dev, "Unsupported dev_id_val (0x%x)\n",
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dev_id_val);
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return -EINVAL;
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}
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dev_dbg(pcie->dev, "dev_id_val: 0x%x\n", dev_id_val);
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return 0;
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}
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static int al_pcie_reg_offsets_set(struct al_pcie *pcie)
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{
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switch (pcie->controller_rev_id) {
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case AL_PCIE_REV_ID_2:
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pcie->reg_offsets.ob_ctrl = OB_CTRL_REV1_2_OFFSET;
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break;
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case AL_PCIE_REV_ID_3:
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case AL_PCIE_REV_ID_4:
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pcie->reg_offsets.ob_ctrl = OB_CTRL_REV3_5_OFFSET;
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break;
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default:
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dev_err(pcie->dev, "Unsupported controller rev_id: 0x%x\n",
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pcie->controller_rev_id);
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return -EINVAL;
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}
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return 0;
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}
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static inline void al_pcie_target_bus_set(struct al_pcie *pcie,
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u8 target_bus,
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u8 mask_target_bus)
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{
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u32 reg;
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reg = FIELD_PREP(CFG_TARGET_BUS_MASK_MASK, mask_target_bus) |
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FIELD_PREP(CFG_TARGET_BUS_BUSNUM_MASK, target_bus);
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al_pcie_controller_writel(pcie, AXI_BASE_OFFSET +
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pcie->reg_offsets.ob_ctrl + CFG_TARGET_BUS,
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reg);
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}
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static void __iomem *al_pcie_conf_addr_map(struct al_pcie *pcie,
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unsigned int busnr,
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unsigned int devfn)
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{
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struct al_pcie_target_bus_cfg *target_bus_cfg = &pcie->target_bus_cfg;
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unsigned int busnr_ecam = busnr & target_bus_cfg->ecam_mask;
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unsigned int busnr_reg = busnr & target_bus_cfg->reg_mask;
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struct pcie_port *pp = &pcie->pci->pp;
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void __iomem *pci_base_addr;
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pci_base_addr = (void __iomem *)((uintptr_t)pp->va_cfg0_base +
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(busnr_ecam << 20) +
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PCIE_ECAM_DEVFN(devfn));
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if (busnr_reg != target_bus_cfg->reg_val) {
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dev_dbg(pcie->pci->dev, "Changing target bus busnum val from 0x%x to 0x%x\n",
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target_bus_cfg->reg_val, busnr_reg);
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target_bus_cfg->reg_val = busnr_reg;
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al_pcie_target_bus_set(pcie,
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target_bus_cfg->reg_val,
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target_bus_cfg->reg_mask);
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}
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return pci_base_addr;
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}
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static int al_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
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unsigned int devfn, int where, int size,
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u32 *val)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct al_pcie *pcie = to_al_pcie(pci);
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unsigned int busnr = bus->number;
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void __iomem *pci_addr;
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int rc;
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pci_addr = al_pcie_conf_addr_map(pcie, busnr, devfn);
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rc = dw_pcie_read(pci_addr + where, size, val);
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dev_dbg(pci->dev, "%d-byte config read from %04x:%02x:%02x.%d offset 0x%x (pci_addr: 0x%px) - val:0x%x\n",
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size, pci_domain_nr(bus), bus->number,
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PCI_SLOT(devfn), PCI_FUNC(devfn), where,
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(pci_addr + where), *val);
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return rc;
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}
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static int al_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
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unsigned int devfn, int where, int size,
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u32 val)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct al_pcie *pcie = to_al_pcie(pci);
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unsigned int busnr = bus->number;
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void __iomem *pci_addr;
|
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int rc;
|
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|
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pci_addr = al_pcie_conf_addr_map(pcie, busnr, devfn);
|
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|
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rc = dw_pcie_write(pci_addr + where, size, val);
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|
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dev_dbg(pci->dev, "%d-byte config write to %04x:%02x:%02x.%d offset 0x%x (pci_addr: 0x%px) - val:0x%x\n",
|
||||
size, pci_domain_nr(bus), bus->number,
|
||||
PCI_SLOT(devfn), PCI_FUNC(devfn), where,
|
||||
(pci_addr + where), val);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static void al_pcie_config_prepare(struct al_pcie *pcie)
|
||||
{
|
||||
struct al_pcie_target_bus_cfg *target_bus_cfg;
|
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struct pcie_port *pp = &pcie->pci->pp;
|
||||
unsigned int ecam_bus_mask;
|
||||
u32 cfg_control_offset;
|
||||
u8 subordinate_bus;
|
||||
u8 secondary_bus;
|
||||
u32 cfg_control;
|
||||
u32 reg;
|
||||
|
||||
target_bus_cfg = &pcie->target_bus_cfg;
|
||||
|
||||
ecam_bus_mask = (pcie->ecam_size >> 20) - 1;
|
||||
if (ecam_bus_mask > 255) {
|
||||
dev_warn(pcie->dev, "ECAM window size is larger than 256MB. Cutting off at 256\n");
|
||||
ecam_bus_mask = 255;
|
||||
}
|
||||
|
||||
/* This portion is taken from the transaction address */
|
||||
target_bus_cfg->ecam_mask = ecam_bus_mask;
|
||||
/* This portion is taken from the cfg_target_bus reg */
|
||||
target_bus_cfg->reg_mask = ~target_bus_cfg->ecam_mask;
|
||||
target_bus_cfg->reg_val = pp->busn->start & target_bus_cfg->reg_mask;
|
||||
|
||||
al_pcie_target_bus_set(pcie, target_bus_cfg->reg_val,
|
||||
target_bus_cfg->reg_mask);
|
||||
|
||||
secondary_bus = pp->busn->start + 1;
|
||||
subordinate_bus = pp->busn->end;
|
||||
|
||||
/* Set the valid values of secondary and subordinate buses */
|
||||
cfg_control_offset = AXI_BASE_OFFSET + pcie->reg_offsets.ob_ctrl +
|
||||
CFG_CONTROL;
|
||||
|
||||
cfg_control = al_pcie_controller_readl(pcie, cfg_control_offset);
|
||||
|
||||
reg = cfg_control &
|
||||
~(CFG_CONTROL_SEC_BUS_MASK | CFG_CONTROL_SUBBUS_MASK);
|
||||
|
||||
reg |= FIELD_PREP(CFG_CONTROL_SUBBUS_MASK, subordinate_bus) |
|
||||
FIELD_PREP(CFG_CONTROL_SEC_BUS_MASK, secondary_bus);
|
||||
|
||||
al_pcie_controller_writel(pcie, cfg_control_offset, reg);
|
||||
}
|
||||
|
||||
static int al_pcie_host_init(struct pcie_port *pp)
|
||||
{
|
||||
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
|
||||
struct al_pcie *pcie = to_al_pcie(pci);
|
||||
int rc;
|
||||
|
||||
rc = al_pcie_rev_id_get(pcie, &pcie->controller_rev_id);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
rc = al_pcie_reg_offsets_set(pcie);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
al_pcie_config_prepare(pcie);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dw_pcie_host_ops al_pcie_host_ops = {
|
||||
.rd_other_conf = al_pcie_rd_other_conf,
|
||||
.wr_other_conf = al_pcie_wr_other_conf,
|
||||
.host_init = al_pcie_host_init,
|
||||
};
|
||||
|
||||
static int al_add_pcie_port(struct pcie_port *pp,
|
||||
struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
int ret;
|
||||
|
||||
pp->ops = &al_pcie_host_ops;
|
||||
|
||||
ret = dw_pcie_host_init(pp);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to initialize host\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dw_pcie_ops dw_pcie_ops = {
|
||||
};
|
||||
|
||||
static int al_pcie_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct resource *controller_res;
|
||||
struct resource *ecam_res;
|
||||
struct resource *dbi_res;
|
||||
struct al_pcie *al_pcie;
|
||||
struct dw_pcie *pci;
|
||||
|
||||
al_pcie = devm_kzalloc(dev, sizeof(*al_pcie), GFP_KERNEL);
|
||||
if (!al_pcie)
|
||||
return -ENOMEM;
|
||||
|
||||
pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
|
||||
if (!pci)
|
||||
return -ENOMEM;
|
||||
|
||||
pci->dev = dev;
|
||||
pci->ops = &dw_pcie_ops;
|
||||
|
||||
al_pcie->pci = pci;
|
||||
al_pcie->dev = dev;
|
||||
|
||||
dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
|
||||
pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_res);
|
||||
if (IS_ERR(pci->dbi_base)) {
|
||||
dev_err(dev, "couldn't remap dbi base %pR\n", dbi_res);
|
||||
return PTR_ERR(pci->dbi_base);
|
||||
}
|
||||
|
||||
ecam_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
|
||||
if (!ecam_res) {
|
||||
dev_err(dev, "couldn't find 'config' reg in DT\n");
|
||||
return -ENOENT;
|
||||
}
|
||||
al_pcie->ecam_size = resource_size(ecam_res);
|
||||
|
||||
controller_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
|
||||
"controller");
|
||||
al_pcie->controller_base = devm_ioremap_resource(dev, controller_res);
|
||||
if (IS_ERR(al_pcie->controller_base)) {
|
||||
dev_err(dev, "couldn't remap controller base %pR\n",
|
||||
controller_res);
|
||||
return PTR_ERR(al_pcie->controller_base);
|
||||
}
|
||||
|
||||
dev_dbg(dev, "From DT: dbi_base: %pR, controller_base: %pR\n",
|
||||
dbi_res, controller_res);
|
||||
|
||||
platform_set_drvdata(pdev, al_pcie);
|
||||
|
||||
return al_add_pcie_port(&pci->pp, pdev);
|
||||
}
|
||||
|
||||
static const struct of_device_id al_pcie_of_match[] = {
|
||||
{ .compatible = "amazon,al-alpine-v2-pcie",
|
||||
},
|
||||
{ .compatible = "amazon,al-alpine-v3-pcie",
|
||||
},
|
||||
{},
|
||||
};
|
||||
|
||||
static struct platform_driver al_pcie_driver = {
|
||||
.driver = {
|
||||
.name = "al-pcie",
|
||||
.of_match_table = al_pcie_of_match,
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
.probe = al_pcie_probe,
|
||||
};
|
||||
builtin_platform_driver(al_pcie_driver);
|
||||
|
||||
#endif /* CONFIG_PCIE_AL*/
|
||||
|
|
|
|||
|
|
@ -531,6 +531,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
|
|||
int ret;
|
||||
u32 reg;
|
||||
void *addr;
|
||||
u8 hdr_type;
|
||||
unsigned int nbars;
|
||||
unsigned int offset;
|
||||
struct pci_epc *epc;
|
||||
|
|
@ -595,6 +596,13 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
|
|||
if (ep->ops->ep_init)
|
||||
ep->ops->ep_init(ep);
|
||||
|
||||
hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE);
|
||||
if (hdr_type != PCI_HEADER_TYPE_NORMAL) {
|
||||
dev_err(pci->dev, "PCIe controller is not set to EP mode (hdr_type:0x%x)!\n",
|
||||
hdr_type);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
|
||||
if (ret < 0)
|
||||
epc->max_functions = 1;
|
||||
|
|
|
|||
|
|
@ -323,6 +323,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
|
|||
struct pci_bus *child;
|
||||
struct pci_host_bridge *bridge;
|
||||
struct resource *cfg_res;
|
||||
u32 hdr_type;
|
||||
int ret;
|
||||
|
||||
raw_spin_lock_init(&pci->pp.lock);
|
||||
|
|
@ -464,6 +465,21 @@ int dw_pcie_host_init(struct pcie_port *pp)
|
|||
goto err_free_msi;
|
||||
}
|
||||
|
||||
ret = dw_pcie_rd_own_conf(pp, PCI_HEADER_TYPE, 1, &hdr_type);
|
||||
if (ret != PCIBIOS_SUCCESSFUL) {
|
||||
dev_err(pci->dev, "Failed reading PCI_HEADER_TYPE cfg space reg (ret: 0x%x)\n",
|
||||
ret);
|
||||
ret = pcibios_err_to_errno(ret);
|
||||
goto err_free_msi;
|
||||
}
|
||||
if (hdr_type != PCI_HEADER_TYPE_BRIDGE) {
|
||||
dev_err(pci->dev,
|
||||
"PCIe controller is not set to bridge type (hdr_type: 0x%x)!\n",
|
||||
hdr_type);
|
||||
ret = -EIO;
|
||||
goto err_free_msi;
|
||||
}
|
||||
|
||||
pp->root_bus_nr = pp->busn->start;
|
||||
|
||||
bridge->dev.parent = dev;
|
||||
|
|
|
|||
|
|
@ -2924,6 +2924,24 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
|
|||
quirk_msi_intx_disable_qca_bug);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
|
||||
quirk_msi_intx_disable_qca_bug);
|
||||
|
||||
/*
|
||||
* Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
|
||||
* should be disabled on platforms where the device (mistakenly) advertises it.
|
||||
*
|
||||
* Notice that this quirk also disables MSI (which may work, but hasn't been
|
||||
* tested), since currently there is no standard way to disable only MSI-X.
|
||||
*
|
||||
* The 0031 device id is reused for other non Root Port device types,
|
||||
* therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
|
||||
*/
|
||||
static void quirk_al_msi_disable(struct pci_dev *dev)
|
||||
{
|
||||
dev->no_msi = 1;
|
||||
pci_warn(dev, "Disabling MSI/MSI-X\n");
|
||||
}
|
||||
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
|
||||
PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable);
|
||||
#endif /* CONFIG_PCI_MSI */
|
||||
|
||||
/*
|
||||
|
|
@ -4365,6 +4383,24 @@ static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags)
|
||||
{
|
||||
if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
|
||||
return -ENOTTY;
|
||||
|
||||
/*
|
||||
* Amazon's Annapurna Labs root ports don't include an ACS capability,
|
||||
* but do include ACS-like functionality. The hardware doesn't support
|
||||
* peer-to-peer transactions via the root port and each has a unique
|
||||
* segment number.
|
||||
*
|
||||
* Additionally, the root ports cannot send traffic to each other.
|
||||
*/
|
||||
acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
|
||||
|
||||
return acs_flags ? 0 : 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
|
||||
* the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
|
||||
|
|
@ -4572,6 +4608,8 @@ static const struct pci_dev_acs_enabled {
|
|||
{ PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
|
||||
{ PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
|
||||
{ PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs },
|
||||
/* Amazon Annapurna Labs */
|
||||
{ PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs },
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -571,6 +571,12 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005f, quirk_blacklist_vpd);
|
|||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, PCI_ANY_ID,
|
||||
quirk_blacklist_vpd);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_QLOGIC, 0x2261, quirk_blacklist_vpd);
|
||||
/*
|
||||
* The Amazon Annapurna Labs 0x0031 device id is reused for other non Root Port
|
||||
* device types, so the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
|
||||
*/
|
||||
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
|
||||
PCI_CLASS_BRIDGE_PCI, 8, quirk_blacklist_vpd);
|
||||
|
||||
/*
|
||||
* For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
|
||||
|
|
|
|||
|
|
@ -2570,6 +2570,8 @@
|
|||
|
||||
#define PCI_VENDOR_ID_ASMEDIA 0x1b21
|
||||
|
||||
#define PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS 0x1c36
|
||||
|
||||
#define PCI_VENDOR_ID_CIRCUITCO 0x1cc8
|
||||
#define PCI_SUBSYSTEM_ID_CIRCUITCO_MINNOWBOARD 0x0001
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue