net: dsa: bcm_sf2: refactor LED regs access
1. Define more regs. Some switches (e.g. BCM4908) have up to 6 regs. 2. Add helper for handling non-lineral port <-> reg mappings. 3. Add support for 12 B LED reg blocks on BCM4908 (different layout) Complete support for LEDs setup will be implemented once Linux receives a proper design & implementation for "hardware" LEDs. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20211229171642.22942-1-zajec5@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Rafał Miłecki
Jakub Kicinski
parent
d6c6d0bb2c
commit
af30f8eaa8
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@ -62,6 +62,38 @@ static u16 bcm_sf2_reg_rgmii_cntrl(struct bcm_sf2_priv *priv, int port)
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return REG_SWITCH_STATUS;
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}
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static u16 bcm_sf2_reg_led_base(struct bcm_sf2_priv *priv, int port)
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{
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switch (port) {
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case 0:
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return REG_LED_0_CNTRL;
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case 1:
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return REG_LED_1_CNTRL;
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case 2:
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return REG_LED_2_CNTRL;
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}
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switch (priv->type) {
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case BCM4908_DEVICE_ID:
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switch (port) {
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case 3:
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return REG_LED_3_CNTRL;
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case 7:
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return REG_LED_4_CNTRL;
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default:
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break;
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}
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break;
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default:
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break;
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}
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WARN_ONCE(1, "Unsupported port %d\n", port);
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/* RO fallback reg */
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return REG_SWITCH_STATUS;
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}
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/* Return the number of active ports, not counting the IMP (CPU) port */
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static unsigned int bcm_sf2_num_active_ports(struct dsa_switch *ds)
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{
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@ -187,9 +219,14 @@ static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
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/* Use PHY-driven LED signaling */
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if (!enable) {
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reg = reg_readl(priv, REG_LED_CNTRL(0));
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reg |= SPDLNK_SRC_SEL;
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reg_writel(priv, reg, REG_LED_CNTRL(0));
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u16 led_ctrl = bcm_sf2_reg_led_base(priv, 0);
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if (priv->type == BCM7278_DEVICE_ID ||
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priv->type == BCM7445_DEVICE_ID) {
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reg = reg_led_readl(priv, led_ctrl, 0);
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reg |= LED_CNTRL_SPDLNK_SRC_SEL;
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reg_led_writel(priv, reg, led_ctrl, 0);
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}
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}
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}
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@ -1232,9 +1269,14 @@ static const u16 bcm_sf2_4908_reg_offsets[] = {
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[REG_SPHY_CNTRL] = 0x24,
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[REG_CROSSBAR] = 0xc8,
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[REG_RGMII_11_CNTRL] = 0x014c,
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[REG_LED_0_CNTRL] = 0x40,
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[REG_LED_1_CNTRL] = 0x4c,
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[REG_LED_2_CNTRL] = 0x58,
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[REG_LED_0_CNTRL] = 0x40,
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[REG_LED_1_CNTRL] = 0x4c,
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[REG_LED_2_CNTRL] = 0x58,
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[REG_LED_3_CNTRL] = 0x64,
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[REG_LED_4_CNTRL] = 0x88,
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[REG_LED_5_CNTRL] = 0xa0,
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[REG_LED_AGGREGATE_CTRL] = 0xb8,
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};
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static const struct bcm_sf2_of_data bcm_sf2_4908_data = {
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@ -210,6 +210,16 @@ SF2_IO_MACRO(acb);
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SWITCH_INTR_L2(0);
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SWITCH_INTR_L2(1);
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static inline u32 reg_led_readl(struct bcm_sf2_priv *priv, u16 off, u16 reg)
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{
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return readl_relaxed(priv->reg + priv->reg_offsets[off] + reg);
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}
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static inline void reg_led_writel(struct bcm_sf2_priv *priv, u32 val, u16 off, u16 reg)
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{
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writel_relaxed(val, priv->reg + priv->reg_offsets[off] + reg);
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}
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/* RXNFC */
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int bcm_sf2_get_rxnfc(struct dsa_switch *ds, int port,
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struct ethtool_rxnfc *nfc, u32 *rule_locs);
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@ -25,6 +25,10 @@ enum bcm_sf2_reg_offs {
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REG_LED_0_CNTRL,
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REG_LED_1_CNTRL,
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REG_LED_2_CNTRL,
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REG_LED_3_CNTRL,
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REG_LED_4_CNTRL,
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REG_LED_5_CNTRL,
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REG_LED_AGGREGATE_CTRL,
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REG_SWITCH_REG_MAX,
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};
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@ -56,6 +60,63 @@ enum bcm_sf2_reg_offs {
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#define CROSSBAR_BCM4908_EXT_GPHY4 1
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#define CROSSBAR_BCM4908_EXT_RGMII 2
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/* Relative to REG_LED_*_CNTRL (BCM7278, BCM7445) */
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#define LED_CNTRL_NO_LINK_ENCODE_SHIFT 0
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#define LED_CNTRL_M10_ENCODE_SHIFT 2
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#define LED_CNTRL_M100_ENCODE_SHIFT 4
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#define LED_CNTRL_M1000_ENCODE_SHIFT 6
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#define LED_CNTRL_SEL_NO_LINK_ENCODE_SHIFT 8
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#define LED_CNTRL_SEL_10M_ENCODE_SHIFT 10
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#define LED_CNTRL_SEL_100M_ENCODE_SHIFT 12
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#define LED_CNTRL_SEL_1000M_ENCODE_SHIFT 14
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#define LED_CNTRL_RX_DV_EN (1 << 16)
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#define LED_CNTRL_TX_EN_EN (1 << 17)
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#define LED_CNTRL_SPDLNK_LED0_ACT_SEL_SHIFT 18
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#define LED_CNTRL_SPDLNK_LED1_ACT_SEL_SHIFT 20
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#define LED_CNTRL_ACT_LED_ACT_SEL_SHIFT 22
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#define LED_CNTRL_SPDLNK_SRC_SEL (1 << 24)
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#define LED_CNTRL_SPDLNK_LED0_ACT_POL_SEL (1 << 25)
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#define LED_CNTRL_SPDLNK_LED1_ACT_POL_SEL (1 << 26)
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#define LED_CNTRL_ACT_LED_POL_SEL (1 << 27)
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#define LED_CNTRL_MASK 0x3
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/* Register relative to REG_LED_*_CNTRL (BCM4908) */
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#define REG_LED_CTRL 0x0
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#define LED_CTRL_RX_ACT_EN 0x00000001
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#define LED_CTRL_TX_ACT_EN 0x00000002
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#define LED_CTRL_SPDLNK_LED0_ACT_SEL 0x00000004
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#define LED_CTRL_SPDLNK_LED1_ACT_SEL 0x00000008
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#define LED_CTRL_SPDLNK_LED2_ACT_SEL 0x00000010
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#define LED_CTRL_ACT_LED_ACT_SEL 0x00000020
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#define LED_CTRL_SPDLNK_LED0_ACT_POL_SEL 0x00000040
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#define LED_CTRL_SPDLNK_LED1_ACT_POL_SEL 0x00000080
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#define LED_CTRL_SPDLNK_LED2_ACT_POL_SEL 0x00000100
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#define LED_CTRL_ACT_LED_POL_SEL 0x00000200
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#define LED_CTRL_LED_SPD_OVRD 0x00001c00
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#define LED_CTRL_LNK_STATUS_OVRD 0x00002000
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#define LED_CTRL_SPD_OVRD_EN 0x00004000
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#define LED_CTRL_LNK_OVRD_EN 0x00008000
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/* Register relative to REG_LED_*_CNTRL (BCM4908) */
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#define REG_LED_LINK_SPEED_ENC_SEL 0x4
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#define LED_LINK_SPEED_ENC_SEL_NO_LINK_SHIFT 0
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#define LED_LINK_SPEED_ENC_SEL_10M_SHIFT 3
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#define LED_LINK_SPEED_ENC_SEL_100M_SHIFT 6
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#define LED_LINK_SPEED_ENC_SEL_1000M_SHIFT 9
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#define LED_LINK_SPEED_ENC_SEL_2500M_SHIFT 12
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#define LED_LINK_SPEED_ENC_SEL_10G_SHIFT 15
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#define LED_LINK_SPEED_ENC_SEL_MASK 0x7
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/* Register relative to REG_LED_*_CNTRL (BCM4908) */
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#define REG_LED_LINK_SPEED_ENC 0x8
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#define LED_LINK_SPEED_ENC_NO_LINK_SHIFT 0
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#define LED_LINK_SPEED_ENC_M10_SHIFT 3
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#define LED_LINK_SPEED_ENC_M100_SHIFT 6
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#define LED_LINK_SPEED_ENC_M1000_SHIFT 9
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#define LED_LINK_SPEED_ENC_M2500_SHIFT 12
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#define LED_LINK_SPEED_ENC_M10G_SHIFT 15
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#define LED_LINK_SPEED_ENC_MASK 0x7
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/* Relative to REG_RGMII_CNTRL */
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#define RGMII_MODE_EN (1 << 0)
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#define ID_MODE_DIS (1 << 1)
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@ -73,10 +134,6 @@ enum bcm_sf2_reg_offs {
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#define LPI_COUNT_SHIFT 9
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#define LPI_COUNT_MASK 0x3F
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#define REG_LED_CNTRL(x) (REG_LED_0_CNTRL + (x))
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#define SPDLNK_SRC_SEL (1 << 24)
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/* Register set relative to 'INTRL2_0' and 'INTRL2_1' */
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#define INTRL2_CPU_STATUS 0x00
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#define INTRL2_CPU_SET 0x04
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