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ASoC: fsl_sai: Add support for i.MX8ULP 

Add i.MX8ULP specific soc data, the max register is FSL_SAI_RTCAP
the IP version is also 0x0301, So version can't be used for the
condition of register FSL_SAI_MCTL setting.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Link: https://lore.kernel.org/r/1652688372-10274-4-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Shengjiu Wang 2022-05-16 16:06:12 +08:00 committed by Mark Brown
parent 2530c5e875
commit af0bd3c0ff
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GPG Key ID: 24D68B725D5487D0
1 changed files with 13 additions and 1 deletions
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14
sound/soc/fsl/fsl_sai.c
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@ -1147,7 +1147,7 @@ static int fsl_sai_probe(struct platform_device *pdev)
/* Select MCLK direction */
if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) &&
sai->verid.version >= 0x0301) {
sai->soc_data->max_register >= FSL_SAI_MCTL) {
regmap_update_bits(sai->regmap, FSL_SAI_MCTL,
FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN);
}
@ -1272,6 +1272,17 @@ static const struct fsl_sai_soc_data fsl_sai_imx8mp_data = {
.max_register = FSL_SAI_MDIV,
};
static const struct fsl_sai_soc_data fsl_sai_imx8ulp_data = {
.use_imx_pcm = true,
.use_edma = true,
.fifo_depth = 16,
.reg_offset = 8,
.mclk0_is_mclk1 = false,
.pins = 4,
.flags = PMQOS_CPU_LATENCY,
.max_register = FSL_SAI_RTCAP,
};
static const struct of_device_id fsl_sai_ids[] = {
{ .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data },
{ .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data },
@ -1281,6 +1292,7 @@ static const struct of_device_id fsl_sai_ids[] = {
{ .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data },
{ .compatible = "fsl,imx8mm-sai", .data = &fsl_sai_imx8mm_data },
{ .compatible = "fsl,imx8mp-sai", .data = &fsl_sai_imx8mp_data },
{ .compatible = "fsl,imx8ulp-sai", .data = &fsl_sai_imx8ulp_data },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, fsl_sai_ids);