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The imx noncritical fixes for 3.10: 

* A bunch of fixes for sparse warings
 * One fix for the typo in use of Kconfig symbol
   MACH_EUKREA_CPUIMX27_USEUART4
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Merge tag 'imx-noncritical-fixes-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/fixes-non-critical

From Shawn Guo:
The imx noncritical fixes for 3.10:

* A bunch of fixes for sparse warings
* One fix for the typo in use of Kconfig symbol
  MACH_EUKREA_CPUIMX27_USEUART4

* tag 'imx-noncritical-fixes-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6:
  ARM: cpuimx27 and mbimx27: prepend CONFIG_ to Kconfig macro
  ARM: mach-imx: mach-imx6q: Fix sparse warnings
  ARM: mach-imx: src: Include "common.h
  ARM: mach-imx: gpc: Include "common.h"
  ARM: mach-imx: avic: Staticize *avic_base
  ARM: mach-imx: tzic: Staticize *tzic_base
  ARM: mach-imx: clk: Include "clk.h"
  ARM: mach-imx: clk-busy: Staticize clk_busy_mux_ops
  ARM: mach-imx: irq-common: Remove imx_irq_set_priority()
  ARM: mach-imx: clk-gate2: Include "clk.h"
  ARM: mach-imx: clk-pllv2: Staticize clk_pllv2_ops
  ARM: mach-imx: clk-pllv1: Staticize clk_pllv1_ops
  ARM: mach-imx: cpu-imx5: Include "common.h"
  ARM: mach-imx: iomux-imx31: Staticize mxc_pin_alloc_map
  ARM: mach-imx: mm-imx3: Staticize imx3_init_l2x0()
  ARM: mach-imx: cpu: Include "common.h"

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2013-04-11 03:04:10 -07:00
parent 7e16063bb8 4f5ef62ced
commit af073c34f3
17 changed files with 19 additions and 32 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/mach-imx/avic.c
View File

@ -51,7 +51,7 @@
#define AVIC_NUM_IRQS 64 #define AVIC_NUM_IRQS 64
void __iomem *avic_base; static void __iomem *avic_base;
static struct irq_domain *domain; static struct irq_domain *domain;
static u32 avic_saved_mask_reg[2]; static u32 avic_saved_mask_reg[2];

2
arch/arm/mach-imx/clk-busy.c
View File

@ -147,7 +147,7 @@ static int clk_busy_mux_set_parent(struct clk_hw *hw, u8 index)
return ret; return ret;
} }
struct clk_ops clk_busy_mux_ops = { static struct clk_ops clk_busy_mux_ops = {
.get_parent = clk_busy_mux_get_parent, .get_parent = clk_busy_mux_get_parent,
.set_parent = clk_busy_mux_set_parent, .set_parent = clk_busy_mux_set_parent,
}; };

1
arch/arm/mach-imx/clk-gate2.c
View File

@ -15,6 +15,7 @@
#include <linux/io.h> #include <linux/io.h>
#include <linux/err.h> #include <linux/err.h>
#include <linux/string.h> #include <linux/string.h>
#include "clk.h"
/** /**
* DOC: basic gatable clock which can gate and ungate it's ouput * DOC: basic gatable clock which can gate and ungate it's ouput

2
arch/arm/mach-imx/clk-pllv1.c
View File

@ -78,7 +78,7 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
return ll; return ll;
} }
struct clk_ops clk_pllv1_ops = { static struct clk_ops clk_pllv1_ops = {
.recalc_rate = clk_pllv1_recalc_rate, .recalc_rate = clk_pllv1_recalc_rate,
}; };

2
arch/arm/mach-imx/clk-pllv2.c
View File

@ -229,7 +229,7 @@ static void clk_pllv2_unprepare(struct clk_hw *hw)
__raw_writel(reg, pllbase + MXC_PLL_DP_CTL); __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
} }
struct clk_ops clk_pllv2_ops = { static struct clk_ops clk_pllv2_ops = {
.prepare = clk_pllv2_prepare, .prepare = clk_pllv2_prepare,
.unprepare = clk_pllv2_unprepare, .unprepare = clk_pllv2_unprepare,
.recalc_rate = clk_pllv2_recalc_rate, .recalc_rate = clk_pllv2_recalc_rate,

1
arch/arm/mach-imx/clk.c
View File

@ -1,3 +1,4 @@
#include <linux/spinlock.h> #include <linux/spinlock.h>
#include "clk.h"
DEFINE_SPINLOCK(imx_ccm_lock); DEFINE_SPINLOCK(imx_ccm_lock);

1
arch/arm/mach-imx/cpu-imx5.c
View File

@ -18,6 +18,7 @@
#include <linux/io.h> #include <linux/io.h>
#include "hardware.h" #include "hardware.h"
#include "common.h"
static int mx5_cpu_rev = -1; static int mx5_cpu_rev = -1;

1
arch/arm/mach-imx/cpu.c
View File

@ -3,6 +3,7 @@
#include <linux/io.h> #include <linux/io.h>
#include "hardware.h" #include "hardware.h"
#include "common.h"
unsigned int __mxc_cpu_type; unsigned int __mxc_cpu_type;
EXPORT_SYMBOL(__mxc_cpu_type); EXPORT_SYMBOL(__mxc_cpu_type);

4
arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
View File

@ -46,7 +46,7 @@ static const int eukrea_mbimx27_pins[] __initconst = {
PE10_PF_UART3_CTS, PE10_PF_UART3_CTS,
PE11_PF_UART3_RTS, PE11_PF_UART3_RTS,
/* UART4 */ /* UART4 */
#if !defined(MACH_EUKREA_CPUIMX27_USEUART4) #if !defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
PB26_AF_UART4_RTS, PB26_AF_UART4_RTS,
PB28_AF_UART4_TXD, PB28_AF_UART4_TXD,
PB29_AF_UART4_CTS, PB29_AF_UART4_CTS,
@ -306,7 +306,7 @@ void __init eukrea_mbimx27_baseboard_init(void)
imx27_add_imx_uart1(&uart_pdata); imx27_add_imx_uart1(&uart_pdata);
imx27_add_imx_uart2(&uart_pdata); imx27_add_imx_uart2(&uart_pdata);
#if !defined(MACH_EUKREA_CPUIMX27_USEUART4) #if !defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
imx27_add_imx_uart3(&uart_pdata); imx27_add_imx_uart3(&uart_pdata);
#endif #endif

1
arch/arm/mach-imx/gpc.c
View File

@ -16,6 +16,7 @@
#include <linux/of_address.h> #include <linux/of_address.h>
#include <linux/of_irq.h> #include <linux/of_irq.h>
#include <linux/irqchip/arm-gic.h> #include <linux/irqchip/arm-gic.h>
#include "common.h"
#define GPC_IMR1 0x008 #define GPC_IMR1 0x008
#define GPC_PGC_CPU_PDN 0x2a0 #define GPC_PGC_CPU_PDN 0x2a0

2
arch/arm/mach-imx/iomux-imx31.c
View File

@ -40,7 +40,7 @@ static DEFINE_SPINLOCK(gpio_mux_lock);
#define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3) #define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3)
unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG]; static unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG];
/* /*
* set the mode for a IOMUX pin. * set the mode for a IOMUX pin.
*/ */

19
arch/arm/mach-imx/irq-common.c
View File

@ -21,25 +21,6 @@
#include "irq-common.h" #include "irq-common.h"
int imx_irq_set_priority(unsigned char irq, unsigned char prio)
{
struct irq_chip_generic *gc;
struct mxc_extra_irq *exirq;
int ret;
ret = -ENOSYS;
gc = irq_get_chip_data(irq);
if (gc && gc->private) {
exirq = gc->private;
if (exirq->set_priority)
ret = exirq->set_priority(irq, prio);
}
return ret;
}
EXPORT_SYMBOL(imx_irq_set_priority);
int mxc_set_irq_fiq(unsigned int irq, unsigned int type) int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
{ {
struct irq_chip_generic *gc; struct irq_chip_generic *gc;

4
arch/arm/mach-imx/mach-cpuimx27.c
View File

@ -48,7 +48,7 @@ static const int eukrea_cpuimx27_pins[] __initconst = {
PE14_PF_UART1_CTS, PE14_PF_UART1_CTS,
PE15_PF_UART1_RTS, PE15_PF_UART1_RTS,
/* UART4 */ /* UART4 */
#if defined(MACH_EUKREA_CPUIMX27_USEUART4) #if defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
PB26_AF_UART4_RTS, PB26_AF_UART4_RTS,
PB28_AF_UART4_TXD, PB28_AF_UART4_TXD,
PB29_AF_UART4_CTS, PB29_AF_UART4_CTS,
@ -272,7 +272,7 @@ static void __init eukrea_cpuimx27_init(void)
/* SDHC2 can be used for Wifi */ /* SDHC2 can be used for Wifi */
imx27_add_mxc_mmc(1, NULL); imx27_add_mxc_mmc(1, NULL);
#endif #endif
#if defined(MACH_EUKREA_CPUIMX27_USEUART4) #if defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
/* in which case UART4 is also used for Bluetooth */ /* in which case UART4 is also used for Bluetooth */
imx27_add_imx_uart3(&uart_pdata); imx27_add_imx_uart3(&uart_pdata);
#endif #endif

4
arch/arm/mach-imx/mach-imx6q.c
View File

@ -73,7 +73,7 @@ static int imx6q_revision(void)
} }
} }
void imx6q_restart(char mode, const char *cmd) static void imx6q_restart(char mode, const char *cmd)
{ {
struct device_node *np; struct device_node *np;
void __iomem *wdog_base; void __iomem *wdog_base;
@ -256,7 +256,7 @@ put_node:
of_node_put(np); of_node_put(np);
} }
struct platform_device imx6q_cpufreq_pdev = { static struct platform_device imx6q_cpufreq_pdev = {
.name = "imx6q-cpufreq", .name = "imx6q-cpufreq",
}; };

2
arch/arm/mach-imx/mm-imx3.c
View File

@ -82,7 +82,7 @@ static void __iomem *imx3_ioremap_caller(unsigned long phys_addr, size_t size,
return __arm_ioremap_caller(phys_addr, size, mtype, caller); return __arm_ioremap_caller(phys_addr, size, mtype, caller);
} }
void __init imx3_init_l2x0(void) static void __init imx3_init_l2x0(void)
{ {
#ifdef CONFIG_CACHE_L2X0 #ifdef CONFIG_CACHE_L2X0
void __iomem *l2x0_base; void __iomem *l2x0_base;

1
arch/arm/mach-imx/src.c
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@ -16,6 +16,7 @@
#include <linux/of_address.h> #include <linux/of_address.h>
#include <linux/smp.h> #include <linux/smp.h>
#include <asm/smp_plat.h> #include <asm/smp_plat.h>
#include "common.h"
#define SRC_SCR 0x000 #define SRC_SCR 0x000
#define SRC_GPR1 0x020 #define SRC_GPR1 0x020

2
arch/arm/mach-imx/tzic.c
View File

@ -49,7 +49,7 @@
#define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */ #define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */
#define TZIC_ID0 0x0FD0 /* Indentification Register 0 */ #define TZIC_ID0 0x0FD0 /* Indentification Register 0 */
void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */ static void __iomem *tzic_base;
static struct irq_domain *domain; static struct irq_domain *domain;
#define TZIC_NUM_IRQS 128 #define TZIC_NUM_IRQS 128