ARM: dts: mvebu: add support for SolidRun Clearfog GTR
SolidRun Clearfog GTR L8 and S4 SBCs are based on Armada 385. They features 8 (L8) or 4 (S4) switched Ethernet ports, 1 1Gb Ethernet port, 1 directly connected SFP port, 1 SFP port behind the switch (not currently described in DT), 3 mini-PCIe slots, eMMC, SPI flash, USB3 port. https://developer.solid-run.com/products/clearfog-gtr-a385/ Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
This commit is contained in:
Baruch Siach
Gregory CLEMENT
parent
e42617b825
commit
aecc313490
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@ -1238,6 +1238,8 @@ dtb-$(CONFIG_MACH_ARMADA_370) += \
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dtb-$(CONFIG_MACH_ARMADA_375) += \
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armada-375-db.dtb
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dtb-$(CONFIG_MACH_ARMADA_38X) += \
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armada-385-clearfog-gtr-s4.dtb \
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armada-385-clearfog-gtr-l8.dtb \
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armada-385-db-88f6820-amc.dtb \
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armada-385-db-ap.dtb \
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armada-385-linksys-caiman.dtb \
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@ -0,0 +1,115 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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#include "armada-385-clearfog-gtr.dtsi"
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/ {
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model = "SolidRun Clearfog GTR L8";
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};
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&mdio {
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switch0: switch0@4 {
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compatible = "marvell,mv88e6190";
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reg = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&cf_gtr_switch_reset_pins>;
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reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@1 {
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reg = <1>;
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label = "lan8";
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phy-handle = <&switch0phy0>;
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};
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port@2 {
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reg = <2>;
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label = "lan7";
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phy-handle = <&switch0phy1>;
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};
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port@3 {
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reg = <3>;
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label = "lan6";
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phy-handle = <&switch0phy2>;
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};
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port@4 {
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reg = <4>;
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label = "lan5";
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phy-handle = <&switch0phy3>;
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};
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port@5 {
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reg = <5>;
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label = "lan4";
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phy-handle = <&switch0phy4>;
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};
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port@6 {
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reg = <6>;
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label = "lan3";
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phy-handle = <&switch0phy5>;
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};
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port@7 {
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reg = <7>;
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label = "lan2";
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phy-handle = <&switch0phy6>;
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};
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port@8 {
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reg = <8>;
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label = "lan1";
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phy-handle = <&switch0phy7>;
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};
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port@10 {
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reg = <10>;
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label = "cpu";
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ethernet = <ð1>;
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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switch0phy0: switch0phy0@1 {
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reg = <0x1>;
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};
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switch0phy1: switch0phy1@2 {
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reg = <0x2>;
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};
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switch0phy2: switch0phy2@3 {
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reg = <0x3>;
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};
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switch0phy3: switch0phy3@4 {
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reg = <0x4>;
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};
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switch0phy4: switch0phy4@5 {
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reg = <0x5>;
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};
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switch0phy5: switch0phy5@6 {
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reg = <0x6>;
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};
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switch0phy6: switch0phy6@7 {
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reg = <0x7>;
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};
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switch0phy7: switch0phy7@8 {
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reg = <0x8>;
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};
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};
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};
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};
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@ -0,0 +1,79 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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#include "armada-385-clearfog-gtr.dtsi"
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/ {
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model = "SolidRun Clearfog GTR S4";
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};
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&sfp0 {
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tx-fault-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
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};
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&mdio {
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switch0: switch0@4 {
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compatible = "marvell,mv88e6085";
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reg = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&cf_gtr_switch_reset_pins>;
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reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@1 {
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reg = <1>;
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label = "lan2";
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phy-handle = <&switch0phy0>;
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};
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port@2 {
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reg = <2>;
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label = "lan1";
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phy-handle = <&switch0phy1>;
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};
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port@3 {
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reg = <3>;
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label = "lan4";
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phy-handle = <&switch0phy2>;
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};
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port@4 {
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reg = <4>;
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label = "lan3";
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phy-handle = <&switch0phy3>;
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};
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port@5 {
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reg = <5>;
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label = "cpu";
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ethernet = <ð1>;
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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switch0phy0: switch0phy0@11 {
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reg = <0x11>;
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};
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switch0phy1: switch0phy1@12 {
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reg = <0x12>;
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};
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switch0phy2: switch0phy2@13 {
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reg = <0x13>;
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};
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switch0phy3: switch0phy3@14 {
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reg = <0x14>;
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};
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};
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};
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};
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@ -0,0 +1,450 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Device Tree file for Clearfog GTR machines rev 1.0 (88F6825)
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*
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* Rabeeh Khoury <rabeeh@solid-run.com>, based on Russell King clearfog work
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*/
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/*
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SERDES mapping -
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0. SATA1 on CON18, or optionally mini PCIe CON3 - PCIe0
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1. 6141 switch (2.5Gbps capable)
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2. SATA0 on CON17, or optionally mini PCIe CON4 - PCIe1
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3. USB 3.0 Host
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4. mini PCIe CON2 - PCIe2
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5. SFP connector, or optionally SGMII Ethernet 1512 PHY
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USB 2.0 mapping -
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0. USB 2.0 - 0 USB pins header CON12
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1. USB 2.0 - 1 mini PCIe CON2
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2. USB 2.0 - 2 to USB 3.0 connector (used with SERDES #3)
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Pin mapping -
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0,1 - console UART
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2,3 - I2C0 - connected to I2C EEPROM, two temperature sensors,
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front panel and PSE controller
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4,5 - MDC/MDIO
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6..17 - RGMII
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18 - Topaz switch reset (active low)
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19 - 1512 phy reset
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20 - 1512 phy reset (eth2, optional)
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21,28,37,38,39,40 - SD0
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22 - USB 3.0 current limiter enable (active high)
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24 - SFP TX fault (input active high)
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25 - SFP present (input active low)
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26,27 - I2C1 - connected to SFP
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29 - Fan PWM
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30 - CON4 mini PCIe wifi disable
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31 - CON3 mini PCIe wifi disable
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32 - Fuse programming power toggle (1.8v)
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33 - CON4 mini PCIe reset
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34 - CON2 mini PCIe wifi disable
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35 - CON3 mini PCIe reset
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36 - Rear button (GPIO active low)
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41 - CON1 front panel connector
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42 - Front LED1, or front panel CON1
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43 - Micron L-PBGA 24 ball SPI (1Gb) CS, or TPM SPI CS
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44 - CON2 mini PCIe reset
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45 - TPM PIRQ signal, or front panel CON1
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46 - SFP TX disable
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47 - Control isolation of boot sensitive SAR signals
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48 - PSE reset
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49 - PSE OSS signal
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50 - PSE interrupt
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52 - Front LED2, or front panel
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53 - Front button
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54 - SFP LOS (input active high)
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55 - Fan sense
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56(mosi),57(clk),58(miso) - SPI interface - 32Mb SPI, 1Gb SPI and TPM
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59 - SPI 32Mb W25Q32BVZPIG CS0 chip select (bootable)
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*/
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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#include "armada-385.dtsi"
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/ {
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compatible = "marvell,armada385", "marvell,armada380";
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aliases {
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/* So that mvebu u-boot can update the MAC addresses */
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ethernet1 = ð0;
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ethernet2 = ð1;
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ethernet3 = ð2;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x10000000>; /* 256 MB */
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "3P3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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reg_5p0v: regulator-5p0v {
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compatible = "regulator-fixed";
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regulator-name = "5P0V";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-always-on;
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};
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v_usb3_con: regulator-v-usb3-con {
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compatible = "regulator-fixed";
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gpio = <&gpio0 22 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&cf_gtr_usb3_con_vbus>;
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regulator-max-microvolt = <5000000>;
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regulator-min-microvolt = <5000000>;
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regulator-name = "v_usb3_con";
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vin-supply = <®_5p0v>;
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regulator-boot-on;
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regulator-always-on;
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
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MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
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MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
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MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
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internal-regs {
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rtc@a3800 {
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status = "okay";
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};
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i2c@11000 { /* ROM, temp sensor and front panel */
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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i2c@11100 { /* SFP (CON5/CON6) */
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pinctrl-0 = <&cf_gtr_i2c1_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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pinctrl@18000 {
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cf_gtr_switch_reset_pins: cf-gtr-switch-reset-pins {
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marvell,pins = "mpp18";
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marvell,function = "gpio";
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};
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cf_gtr_usb3_con_vbus: cf-gtr-usb3-con-vbus {
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marvell,pins = "mpp22";
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marvell,function = "gpio";
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};
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cf_gtr_fan_pwm: cf-gtr-fan-pwm {
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marvell,pins = "mpp23";
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marvell,function = "gpio";
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};
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cf_gtr_i2c1_pins: i2c1-pins {
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/* SFP */
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marvell,pins = "mpp26", "mpp27";
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marvell,function = "i2c1";
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};
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cf_gtr_sdhci_pins: cf-gtr-sdhci-pins {
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marvell,pins = "mpp21", "mpp28",
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"mpp37", "mpp38",
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"mpp39", "mpp40";
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marvell,function = "sd0";
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};
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cf_gtr_isolation_pins: cf-gtr-isolation-pins {
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marvell,pins = "mpp47";
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marvell,function = "gpio";
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};
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cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins {
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marvell,pins = "mpp48";
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marvell,function = "gpio";
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};
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cf_gtr_spi1_cs_pins: spi1-cs-pins {
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marvell,pins = "mpp59";
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marvell,function = "spi1";
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};
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cf_gtr_front_button_pins: cf-gtr-front-button-pins {
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marvell,pins = "mpp53";
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marvell,function = "gpio";
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};
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cf_gtr_rear_button_pins: cf-gtr-rear-button-pins {
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marvell,pins = "mpp36";
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marvell,function = "gpio";
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};
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};
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sdhci@d8000 {
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bus-width = <4>;
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no-1-8-v;
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non-removable;
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pinctrl-0 = <&cf_gtr_sdhci_pins>;
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pinctrl-names = "default";
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status = "okay";
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vmmc = <®_3p3v>;
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wp-inverted;
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};
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usb@58000 {
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status = "okay";
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};
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usb3@f0000 {
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status = "okay";
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};
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usb3@f8000 {
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vbus-supply = <&v_usb3_con>;
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status = "okay";
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};
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};
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pcie {
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status = "okay";
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/*
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* The PCIe units are accessible through
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* the mini-PCIe connectors on the board.
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*/
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pcie@1,0 {
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reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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pcie@2,0 {
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reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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pcie@3,0 {
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reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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};
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};
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sfp0: sfp {
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compatible = "sff,sfp";
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i2c-bus = <&i2c1>;
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los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio0 25 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
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};
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gpio-keys {
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compatible = "gpio-keys";
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pinctrl-0 = <&cf_gtr_rear_button_pins &cf_gtr_front_button_pins>;
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pinctrl-names = "default";
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button_0 {
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label = "Rear Button";
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gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
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linux,can-disable;
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linux,code = <BTN_0>;
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};
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button_1 {
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label = "Front Button";
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gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
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linux,can-disable;
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linux,code = <BTN_1>;
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};
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};
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gpio-leds {
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compatible = "gpio-leds";
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led1 {
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function = LED_FUNCTION_CPU;
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color = <LED_COLOR_ID_GREEN>;
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gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
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};
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led2 {
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function = LED_FUNCTION_HEARTBEAT;
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color = <LED_COLOR_ID_GREEN>;
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gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
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};
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};
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};
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&bm {
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status = "okay";
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};
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&bm_bppi {
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status = "okay";
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||||
};
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ð0 {
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/* ethernet@70000 */
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pinctrl-0 = <&ge0_rgmii_pins>;
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pinctrl-names = "default";
|
||||
phy = <&phy_dedicated>;
|
||||
phy-mode = "rgmii-id";
|
||||
buffer-manager = <&bm>;
|
||||
bm,pool-long = <0>;
|
||||
bm,pool-short = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ð1 {
|
||||
/* ethernet@30000 */
|
||||
bm,pool-long = <2>;
|
||||
bm,pool-short = <1>;
|
||||
buffer-manager = <&bm>;
|
||||
phys = <&comphy1 1>;
|
||||
phy-mode = "2500base-x";
|
||||
status = "okay";
|
||||
|
||||
fixed-link {
|
||||
speed = <2500>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
ð2 {
|
||||
/* ethernet@34000 */
|
||||
bm,pool-long = <3>;
|
||||
bm,pool-short = <1>;
|
||||
buffer-manager = <&bm>;
|
||||
managed = "in-band-status";
|
||||
phys = <&comphy5 1>;
|
||||
phy-mode = "sgmii";
|
||||
sfp = <&sfp0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
status = "okay";
|
||||
|
||||
phy_dedicated: ethernet-phy@0 {
|
||||
/*
|
||||
* Annoyingly, the marvell phy driver configures the LED
|
||||
* register, rather than preserving reset-loaded setting.
|
||||
* We undo that rubbish here.
|
||||
*/
|
||||
marvell,reg-init = <3 16 0 0x1017>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
/*
|
||||
* CS0: W25Q32 flash
|
||||
*/
|
||||
pinctrl-0 = <&spi1_pins &cf_gtr_spi1_cs_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "w25q32", "jedec,spi-nor";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <3000000>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
/* U26 temperature sensor placed near SoC */
|
||||
temp1: nct75@4c {
|
||||
compatible = "lm75";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
|
||||
/* U27 temperature sensor placed near RTC battery */
|
||||
temp2: nct75@4d {
|
||||
compatible = "lm75";
|
||||
reg = <0x4d>;
|
||||
};
|
||||
|
||||
/* 2Kb eeprom */
|
||||
eeprom@53 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x53>;
|
||||
};
|
||||
};
|
||||
|
||||
&ahci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ahci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
pinctrl-0 = <&cf_gtr_fan_pwm>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
wifi-disable {
|
||||
gpio-hog;
|
||||
gpios = <30 GPIO_ACTIVE_LOW>, <31 GPIO_ACTIVE_LOW>;
|
||||
output-low;
|
||||
line-name = "wifi-disable";
|
||||
};
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
lte-disable {
|
||||
gpio-hog;
|
||||
gpios = <2 GPIO_ACTIVE_LOW>;
|
||||
output-low;
|
||||
line-name = "lte-disable";
|
||||
};
|
||||
|
||||
/*
|
||||
* This signal, when asserted, isolates Armada 38x sample at reset pins
|
||||
* from control of external devices. Should be de-asserted after reset.
|
||||
*/
|
||||
sar-isolation {
|
||||
gpio-hog;
|
||||
gpios = <15 GPIO_ACTIVE_LOW>;
|
||||
output-low;
|
||||
line-name = "sar-isolation";
|
||||
};
|
||||
|
||||
poe-reset {
|
||||
gpio-hog;
|
||||
gpios = <16 GPIO_ACTIVE_LOW>;
|
||||
output-low;
|
||||
line-name = "poe-reset";
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue