drm/amdgpu: drop redundant vi_mqd define
Vi_structs.h has defined vi_mqd, drop redundant vi_mqd define. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Xiangliang Yu
Alex Deucher
parent
47e50d5c0d
commit
aeab203205
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@ -25,6 +25,7 @@
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#include "amdgpu.h"
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#include "amdgpu_gfx.h"
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#include "vi.h"
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#include "vi_structs.h"
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#include "vid.h"
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#include "amdgpu_ucode.h"
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#include "amdgpu_atombios.h"
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@ -4469,267 +4470,6 @@ static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
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return 0;
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}
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struct vi_mqd {
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uint32_t header; /* ordinal0 */
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uint32_t compute_dispatch_initiator; /* ordinal1 */
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uint32_t compute_dim_x; /* ordinal2 */
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uint32_t compute_dim_y; /* ordinal3 */
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uint32_t compute_dim_z; /* ordinal4 */
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uint32_t compute_start_x; /* ordinal5 */
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uint32_t compute_start_y; /* ordinal6 */
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uint32_t compute_start_z; /* ordinal7 */
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uint32_t compute_num_thread_x; /* ordinal8 */
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uint32_t compute_num_thread_y; /* ordinal9 */
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uint32_t compute_num_thread_z; /* ordinal10 */
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uint32_t compute_pipelinestat_enable; /* ordinal11 */
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uint32_t compute_perfcount_enable; /* ordinal12 */
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uint32_t compute_pgm_lo; /* ordinal13 */
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uint32_t compute_pgm_hi; /* ordinal14 */
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uint32_t compute_tba_lo; /* ordinal15 */
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uint32_t compute_tba_hi; /* ordinal16 */
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uint32_t compute_tma_lo; /* ordinal17 */
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uint32_t compute_tma_hi; /* ordinal18 */
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uint32_t compute_pgm_rsrc1; /* ordinal19 */
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uint32_t compute_pgm_rsrc2; /* ordinal20 */
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uint32_t compute_vmid; /* ordinal21 */
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uint32_t compute_resource_limits; /* ordinal22 */
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uint32_t compute_static_thread_mgmt_se0; /* ordinal23 */
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uint32_t compute_static_thread_mgmt_se1; /* ordinal24 */
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uint32_t compute_tmpring_size; /* ordinal25 */
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uint32_t compute_static_thread_mgmt_se2; /* ordinal26 */
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uint32_t compute_static_thread_mgmt_se3; /* ordinal27 */
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uint32_t compute_restart_x; /* ordinal28 */
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uint32_t compute_restart_y; /* ordinal29 */
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uint32_t compute_restart_z; /* ordinal30 */
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uint32_t compute_thread_trace_enable; /* ordinal31 */
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uint32_t compute_misc_reserved; /* ordinal32 */
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uint32_t compute_dispatch_id; /* ordinal33 */
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uint32_t compute_threadgroup_id; /* ordinal34 */
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uint32_t compute_relaunch; /* ordinal35 */
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uint32_t compute_wave_restore_addr_lo; /* ordinal36 */
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uint32_t compute_wave_restore_addr_hi; /* ordinal37 */
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uint32_t compute_wave_restore_control; /* ordinal38 */
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uint32_t reserved9; /* ordinal39 */
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uint32_t reserved10; /* ordinal40 */
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uint32_t reserved11; /* ordinal41 */
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uint32_t reserved12; /* ordinal42 */
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uint32_t reserved13; /* ordinal43 */
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uint32_t reserved14; /* ordinal44 */
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uint32_t reserved15; /* ordinal45 */
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uint32_t reserved16; /* ordinal46 */
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uint32_t reserved17; /* ordinal47 */
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uint32_t reserved18; /* ordinal48 */
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uint32_t reserved19; /* ordinal49 */
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uint32_t reserved20; /* ordinal50 */
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uint32_t reserved21; /* ordinal51 */
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uint32_t reserved22; /* ordinal52 */
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uint32_t reserved23; /* ordinal53 */
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uint32_t reserved24; /* ordinal54 */
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uint32_t reserved25; /* ordinal55 */
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uint32_t reserved26; /* ordinal56 */
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uint32_t reserved27; /* ordinal57 */
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uint32_t reserved28; /* ordinal58 */
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uint32_t reserved29; /* ordinal59 */
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uint32_t reserved30; /* ordinal60 */
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uint32_t reserved31; /* ordinal61 */
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uint32_t reserved32; /* ordinal62 */
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uint32_t reserved33; /* ordinal63 */
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uint32_t reserved34; /* ordinal64 */
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uint32_t compute_user_data_0; /* ordinal65 */
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uint32_t compute_user_data_1; /* ordinal66 */
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uint32_t compute_user_data_2; /* ordinal67 */
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uint32_t compute_user_data_3; /* ordinal68 */
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uint32_t compute_user_data_4; /* ordinal69 */
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uint32_t compute_user_data_5; /* ordinal70 */
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uint32_t compute_user_data_6; /* ordinal71 */
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uint32_t compute_user_data_7; /* ordinal72 */
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uint32_t compute_user_data_8; /* ordinal73 */
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uint32_t compute_user_data_9; /* ordinal74 */
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uint32_t compute_user_data_10; /* ordinal75 */
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uint32_t compute_user_data_11; /* ordinal76 */
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uint32_t compute_user_data_12; /* ordinal77 */
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uint32_t compute_user_data_13; /* ordinal78 */
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uint32_t compute_user_data_14; /* ordinal79 */
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uint32_t compute_user_data_15; /* ordinal80 */
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uint32_t cp_compute_csinvoc_count_lo; /* ordinal81 */
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uint32_t cp_compute_csinvoc_count_hi; /* ordinal82 */
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uint32_t reserved35; /* ordinal83 */
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uint32_t reserved36; /* ordinal84 */
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uint32_t reserved37; /* ordinal85 */
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uint32_t cp_mqd_query_time_lo; /* ordinal86 */
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uint32_t cp_mqd_query_time_hi; /* ordinal87 */
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uint32_t cp_mqd_connect_start_time_lo; /* ordinal88 */
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uint32_t cp_mqd_connect_start_time_hi; /* ordinal89 */
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uint32_t cp_mqd_connect_end_time_lo; /* ordinal90 */
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uint32_t cp_mqd_connect_end_time_hi; /* ordinal91 */
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uint32_t cp_mqd_connect_end_wf_count; /* ordinal92 */
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uint32_t cp_mqd_connect_end_pq_rptr; /* ordinal93 */
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uint32_t cp_mqd_connect_end_pq_wptr; /* ordinal94 */
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uint32_t cp_mqd_connect_end_ib_rptr; /* ordinal95 */
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uint32_t reserved38; /* ordinal96 */
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uint32_t reserved39; /* ordinal97 */
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uint32_t cp_mqd_save_start_time_lo; /* ordinal98 */
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uint32_t cp_mqd_save_start_time_hi; /* ordinal99 */
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uint32_t cp_mqd_save_end_time_lo; /* ordinal100 */
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uint32_t cp_mqd_save_end_time_hi; /* ordinal101 */
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uint32_t cp_mqd_restore_start_time_lo; /* ordinal102 */
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uint32_t cp_mqd_restore_start_time_hi; /* ordinal103 */
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uint32_t cp_mqd_restore_end_time_lo; /* ordinal104 */
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uint32_t cp_mqd_restore_end_time_hi; /* ordinal105 */
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uint32_t reserved40; /* ordinal106 */
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uint32_t reserved41; /* ordinal107 */
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uint32_t gds_cs_ctxsw_cnt0; /* ordinal108 */
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uint32_t gds_cs_ctxsw_cnt1; /* ordinal109 */
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uint32_t gds_cs_ctxsw_cnt2; /* ordinal110 */
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uint32_t gds_cs_ctxsw_cnt3; /* ordinal111 */
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uint32_t reserved42; /* ordinal112 */
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uint32_t reserved43; /* ordinal113 */
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uint32_t cp_pq_exe_status_lo; /* ordinal114 */
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uint32_t cp_pq_exe_status_hi; /* ordinal115 */
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uint32_t cp_packet_id_lo; /* ordinal116 */
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uint32_t cp_packet_id_hi; /* ordinal117 */
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uint32_t cp_packet_exe_status_lo; /* ordinal118 */
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uint32_t cp_packet_exe_status_hi; /* ordinal119 */
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uint32_t gds_save_base_addr_lo; /* ordinal120 */
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uint32_t gds_save_base_addr_hi; /* ordinal121 */
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uint32_t gds_save_mask_lo; /* ordinal122 */
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uint32_t gds_save_mask_hi; /* ordinal123 */
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uint32_t ctx_save_base_addr_lo; /* ordinal124 */
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uint32_t ctx_save_base_addr_hi; /* ordinal125 */
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uint32_t reserved44; /* ordinal126 */
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uint32_t reserved45; /* ordinal127 */
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uint32_t cp_mqd_base_addr_lo; /* ordinal128 */
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uint32_t cp_mqd_base_addr_hi; /* ordinal129 */
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uint32_t cp_hqd_active; /* ordinal130 */
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uint32_t cp_hqd_vmid; /* ordinal131 */
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uint32_t cp_hqd_persistent_state; /* ordinal132 */
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uint32_t cp_hqd_pipe_priority; /* ordinal133 */
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uint32_t cp_hqd_queue_priority; /* ordinal134 */
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uint32_t cp_hqd_quantum; /* ordinal135 */
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uint32_t cp_hqd_pq_base_lo; /* ordinal136 */
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uint32_t cp_hqd_pq_base_hi; /* ordinal137 */
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uint32_t cp_hqd_pq_rptr; /* ordinal138 */
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uint32_t cp_hqd_pq_rptr_report_addr_lo; /* ordinal139 */
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uint32_t cp_hqd_pq_rptr_report_addr_hi; /* ordinal140 */
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uint32_t cp_hqd_pq_wptr_poll_addr; /* ordinal141 */
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uint32_t cp_hqd_pq_wptr_poll_addr_hi; /* ordinal142 */
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uint32_t cp_hqd_pq_doorbell_control; /* ordinal143 */
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uint32_t cp_hqd_pq_wptr; /* ordinal144 */
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uint32_t cp_hqd_pq_control; /* ordinal145 */
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uint32_t cp_hqd_ib_base_addr_lo; /* ordinal146 */
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uint32_t cp_hqd_ib_base_addr_hi; /* ordinal147 */
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uint32_t cp_hqd_ib_rptr; /* ordinal148 */
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uint32_t cp_hqd_ib_control; /* ordinal149 */
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uint32_t cp_hqd_iq_timer; /* ordinal150 */
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uint32_t cp_hqd_iq_rptr; /* ordinal151 */
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uint32_t cp_hqd_dequeue_request; /* ordinal152 */
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uint32_t cp_hqd_dma_offload; /* ordinal153 */
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uint32_t cp_hqd_sema_cmd; /* ordinal154 */
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uint32_t cp_hqd_msg_type; /* ordinal155 */
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uint32_t cp_hqd_atomic0_preop_lo; /* ordinal156 */
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uint32_t cp_hqd_atomic0_preop_hi; /* ordinal157 */
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uint32_t cp_hqd_atomic1_preop_lo; /* ordinal158 */
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uint32_t cp_hqd_atomic1_preop_hi; /* ordinal159 */
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uint32_t cp_hqd_hq_status0; /* ordinal160 */
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uint32_t cp_hqd_hq_control0; /* ordinal161 */
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uint32_t cp_mqd_control; /* ordinal162 */
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uint32_t cp_hqd_hq_status1; /* ordinal163 */
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uint32_t cp_hqd_hq_control1; /* ordinal164 */
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uint32_t cp_hqd_eop_base_addr_lo; /* ordinal165 */
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uint32_t cp_hqd_eop_base_addr_hi; /* ordinal166 */
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uint32_t cp_hqd_eop_control; /* ordinal167 */
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uint32_t cp_hqd_eop_rptr; /* ordinal168 */
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uint32_t cp_hqd_eop_wptr; /* ordinal169 */
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uint32_t cp_hqd_eop_done_events; /* ordinal170 */
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uint32_t cp_hqd_ctx_save_base_addr_lo; /* ordinal171 */
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uint32_t cp_hqd_ctx_save_base_addr_hi; /* ordinal172 */
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uint32_t cp_hqd_ctx_save_control; /* ordinal173 */
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uint32_t cp_hqd_cntl_stack_offset; /* ordinal174 */
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uint32_t cp_hqd_cntl_stack_size; /* ordinal175 */
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uint32_t cp_hqd_wg_state_offset; /* ordinal176 */
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uint32_t cp_hqd_ctx_save_size; /* ordinal177 */
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uint32_t cp_hqd_gds_resource_state; /* ordinal178 */
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uint32_t cp_hqd_error; /* ordinal179 */
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uint32_t cp_hqd_eop_wptr_mem; /* ordinal180 */
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uint32_t cp_hqd_eop_dones; /* ordinal181 */
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uint32_t reserved46; /* ordinal182 */
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uint32_t reserved47; /* ordinal183 */
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uint32_t reserved48; /* ordinal184 */
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uint32_t reserved49; /* ordinal185 */
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uint32_t reserved50; /* ordinal186 */
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uint32_t reserved51; /* ordinal187 */
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uint32_t reserved52; /* ordinal188 */
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uint32_t reserved53; /* ordinal189 */
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uint32_t reserved54; /* ordinal190 */
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uint32_t reserved55; /* ordinal191 */
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uint32_t iqtimer_pkt_header; /* ordinal192 */
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uint32_t iqtimer_pkt_dw0; /* ordinal193 */
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uint32_t iqtimer_pkt_dw1; /* ordinal194 */
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uint32_t iqtimer_pkt_dw2; /* ordinal195 */
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uint32_t iqtimer_pkt_dw3; /* ordinal196 */
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uint32_t iqtimer_pkt_dw4; /* ordinal197 */
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uint32_t iqtimer_pkt_dw5; /* ordinal198 */
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uint32_t iqtimer_pkt_dw6; /* ordinal199 */
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uint32_t iqtimer_pkt_dw7; /* ordinal200 */
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uint32_t iqtimer_pkt_dw8; /* ordinal201 */
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uint32_t iqtimer_pkt_dw9; /* ordinal202 */
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uint32_t iqtimer_pkt_dw10; /* ordinal203 */
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uint32_t iqtimer_pkt_dw11; /* ordinal204 */
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uint32_t iqtimer_pkt_dw12; /* ordinal205 */
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uint32_t iqtimer_pkt_dw13; /* ordinal206 */
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uint32_t iqtimer_pkt_dw14; /* ordinal207 */
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uint32_t iqtimer_pkt_dw15; /* ordinal208 */
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uint32_t iqtimer_pkt_dw16; /* ordinal209 */
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uint32_t iqtimer_pkt_dw17; /* ordinal210 */
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uint32_t iqtimer_pkt_dw18; /* ordinal211 */
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uint32_t iqtimer_pkt_dw19; /* ordinal212 */
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uint32_t iqtimer_pkt_dw20; /* ordinal213 */
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uint32_t iqtimer_pkt_dw21; /* ordinal214 */
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uint32_t iqtimer_pkt_dw22; /* ordinal215 */
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uint32_t iqtimer_pkt_dw23; /* ordinal216 */
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uint32_t iqtimer_pkt_dw24; /* ordinal217 */
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uint32_t iqtimer_pkt_dw25; /* ordinal218 */
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uint32_t iqtimer_pkt_dw26; /* ordinal219 */
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uint32_t iqtimer_pkt_dw27; /* ordinal220 */
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uint32_t iqtimer_pkt_dw28; /* ordinal221 */
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uint32_t iqtimer_pkt_dw29; /* ordinal222 */
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uint32_t iqtimer_pkt_dw30; /* ordinal223 */
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uint32_t iqtimer_pkt_dw31; /* ordinal224 */
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uint32_t reserved56; /* ordinal225 */
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uint32_t reserved57; /* ordinal226 */
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uint32_t reserved58; /* ordinal227 */
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uint32_t set_resources_header; /* ordinal228 */
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uint32_t set_resources_dw1; /* ordinal229 */
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uint32_t set_resources_dw2; /* ordinal230 */
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uint32_t set_resources_dw3; /* ordinal231 */
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uint32_t set_resources_dw4; /* ordinal232 */
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uint32_t set_resources_dw5; /* ordinal233 */
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uint32_t set_resources_dw6; /* ordinal234 */
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uint32_t set_resources_dw7; /* ordinal235 */
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uint32_t reserved59; /* ordinal236 */
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uint32_t reserved60; /* ordinal237 */
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uint32_t reserved61; /* ordinal238 */
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uint32_t reserved62; /* ordinal239 */
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uint32_t reserved63; /* ordinal240 */
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uint32_t reserved64; /* ordinal241 */
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uint32_t reserved65; /* ordinal242 */
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uint32_t reserved66; /* ordinal243 */
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uint32_t reserved67; /* ordinal244 */
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uint32_t reserved68; /* ordinal245 */
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uint32_t reserved69; /* ordinal246 */
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uint32_t reserved70; /* ordinal247 */
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uint32_t reserved71; /* ordinal248 */
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uint32_t reserved72; /* ordinal249 */
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uint32_t reserved73; /* ordinal250 */
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uint32_t reserved74; /* ordinal251 */
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uint32_t reserved75; /* ordinal252 */
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uint32_t reserved76; /* ordinal253 */
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uint32_t reserved77; /* ordinal254 */
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uint32_t reserved78; /* ordinal255 */
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uint32_t reserved_t[256]; /* Reserve 256 dword buffer used by ucode */
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};
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static void gfx_v8_0_cp_compute_fini(struct amdgpu_device *adev)
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{
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int i, r;
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@ -4914,9 +4654,9 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
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/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
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wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
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mqd->cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
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mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
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mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
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WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr);
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WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr_lo);
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WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
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mqd->cp_hqd_pq_wptr_poll_addr_hi);
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