ARM: DT changes for 5.19, part 1
There are 40 branches this time, adding a lot of new hardware
support, and cleanups. Krzysztof Kozlowski continues his treewide
cleanups.
There are a number of new SoCs, all of them as part of existing
families, and typically added along with a reference board:
- Renesas RZ/G2UL (R9A07G043) is the single-core version of the RZ/G2L
general-purpose MPU.
- Renesas RZ/V2M (R9A09G011) is a smart camera SoC
- Renesas R-Car V4H (R8A779G0) is an automotive chip with Cortex-A76
cores and deep learning accerlation.
- Broadcom BCM47622 is a new broadband SoC based on a quad Cortex-A7
and dual Wifi-6.
- Corstone1000 is a generic platform from Arm that is used for designing
custom SoCs, the support for now is for the Fixed Virtual Platform
emulation for it.
- Mediatek MT8195 (Kompanio 1200) is a high-end consumer chip used
in upcoming Chromebooks.
- NXP i.MXRT1050 is a Cortex-M7 based microcontroller, the first
MMU-less SoC to be added in a while
New machines based on already supported SoCs this time are mainly
for 32-bit platforms and include:
- Two wireless routers based on Broadcom bcm4708
- 30 new boards based on NXP i.MX6, i.MX7 and i.MX8 families, mostly
for the industrial embedded market, and on NXP LS1021A based
IOT board.
- Two ethernet switches based on Microchip LAN966
- Eight Qualcomm Snapdragon based machines, including a smartwatch,
a Chromebook board and some phones
- Another phone based on the old ST-Ericsson Ux500 platform
- Seven STM32MP1 based boards
- Four single-board computers based on Rockchip RK3566/RK3568
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Merge tag 'arm-dt-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM DT updates from Arnd Bergmann:
"There are 40 branches this time, adding a lot of new hardware support,
and cleanups. Krzysztof Kozlowski continues his treewide cleanups.
There are a number of new SoCs, all of them as part of existing
families, and typically added along with a reference board:
- Renesas RZ/G2UL (R9A07G043) is the single-core version of the
RZ/G2L general-purpose MPU.
- Renesas RZ/V2M (R9A09G011) is a smart camera SoC
- Renesas R-Car V4H (R8A779G0) is an automotive chip with Cortex-A76
cores and deep learning accerlation.
- Broadcom BCM47622 is a new broadband SoC based on a quad Cortex-A7
and dual Wifi-6.
- Corstone1000 is a generic platform from Arm that is used for
designing custom SoCs, the support for now is for the Fixed Virtual
Platform emulation for it.
- Mediatek MT8195 (Kompanio 1200) is a high-end consumer chip used in
upcoming Chromebooks.
- NXP i.MXRT1050 is a Cortex-M7 based microcontroller, the first
MMU-less SoC to be added in a while
New machines based on already supported SoCs this time are mainly for
32-bit platforms and include:
- Two wireless routers based on Broadcom bcm4708
- 30 new boards based on NXP i.MX6, i.MX7 and i.MX8 families, mostly
for the industrial embedded market, and on NXP LS1021A based IOT
board.
- Two ethernet switches based on Microchip LAN966
- Eight Qualcomm Snapdragon based machines, including a smartwatch, a
Chromebook board and some phones
- Another phone based on the old ST-Ericsson Ux500 platform
- Seven STM32MP1 based boards
- Four single-board computers based on Rockchip RK3566/RK3568"
* tag 'arm-dt-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (791 commits)
ARM: dts: kswitch-d10: enable networking
ARM: dts: lan966x: add switch node
ARM: dts: lan966x: add serdes node
ARM: dts: lan966x: add reset switch reset node
ARM: dts: lan966x: add MIIM nodes
ARM: dts: lan966x: add hwmon node
ARM: dts: lan966x: add basic Kontron KSwitch D10 support
ARM: dts: lan966x: add flexcom I2C nodes
ARM: dts: lan966x: add flexcom SPI nodes
ARM: dts: lan966x: add all flexcom usart nodes
ARM: dts: lan966x: add missing uart DMA channel
ARM: dts: lan966x: add sgpio node
ARM: dts: lan966x: swap dma channels for crypto node
ARM: dts: lan966x: rename pinctrl nodes
ARM: dts: at91: sama7g5: remove interrupt-parent from gic node
ARM: dts: at91: use generic node name for dataflash
ARM: dts: turris-omnia: Add atsha204a node
arm64: dts: mt8192: Follow binding order for SCP registers
arm64: dts: mediatek: add mtk-snfi for mt7622
arm64: dts: mediatek: mt8195-demo: enable uart1
...
This commit is contained in:
Linus Torvalds
commit
ae86218328
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@ -0,0 +1,45 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/arm,corstone1000.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM Corstone1000 Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Vishnu Banavath <vishnu.banavath@arm.com>
|
||||
- Rui Miguel Silva <rui.silva@linaro.org>
|
||||
|
||||
description: |+
|
||||
ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that
|
||||
provides a flexible compute architecture that combines Cortex‑A and Cortex‑M
|
||||
processors.
|
||||
|
||||
Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion
|
||||
systems for M-Class (or other) processors for adding sensors, connectivity,
|
||||
video, audio and machine learning at the edge System and security IPs to build
|
||||
a secure SoC for a range of rich IoT applications, for example gateways, smart
|
||||
cameras and embedded systems.
|
||||
|
||||
Integrated Secure Enclave providing hardware Root of Trust and supporting
|
||||
seamless integration of the optional CryptoCell™-312 cryptographic
|
||||
accelerator.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: Corstone1000 MPS3 it has 1 Cortex-A35 CPU core in a FPGA
|
||||
implementation of the Corstone1000 in the MPS3 prototyping board. See
|
||||
ARM document DAI0550.
|
||||
items:
|
||||
- const: arm,corstone1000-mps3
|
||||
- description: Corstone1000 FVP is the Fixed Virtual Platform
|
||||
implementation of this system. See ARM ecosystems FVP's.
|
||||
items:
|
||||
- const: arm,corstone1000-fvp
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
|
|
@ -64,6 +64,7 @@ properties:
|
|||
- description: BCM47094 based boards
|
||||
items:
|
||||
- enum:
|
||||
- asus,rt-ac88u
|
||||
- dlink,dir-885l
|
||||
- linksys,panamera
|
||||
- luxul,abr-4500-v1
|
||||
|
|
@ -83,9 +84,14 @@ properties:
|
|||
- brcm,bcm953012er
|
||||
- brcm,bcm953012hr
|
||||
- brcm,bcm953012k
|
||||
- const: brcm,bcm53012
|
||||
- const: brcm,bcm4708
|
||||
|
||||
- description: BCM53016 based boards
|
||||
items:
|
||||
- enum:
|
||||
- meraki,mr32
|
||||
- const: brcm,brcm53012
|
||||
- const: brcm,brcm53016
|
||||
- const: brcm,bcm53016
|
||||
- const: brcm,bcm4708
|
||||
|
||||
additionalProperties: true
|
||||
|
|
|
|||
|
|
@ -0,0 +1,33 @@
|
|||
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcmbca.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom Broadband SoC device tree bindings
|
||||
|
||||
description:
|
||||
Broadcom Broadband SoCs include family of high performance DSL/PON/Wireless
|
||||
chips that can be used as home gateway, router and WLAN AP for residential,
|
||||
enterprise and carrier applications.
|
||||
|
||||
maintainers:
|
||||
- William Zhang <william.zhang@broadcom.com>
|
||||
- Anand Gore <anand.gore@broadcom.com>
|
||||
- Kursad Oney <kursad.oney@broadcom.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: BCM47622 based boards
|
||||
items:
|
||||
- enum:
|
||||
- brcm,bcm947622
|
||||
- const: brcm,bcm47622
|
||||
- const: brcm,bcmbca
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
|
|
@ -172,7 +172,7 @@ properties:
|
|||
- karo,tx53 # Ka-Ro electronics TX53 module
|
||||
- kiebackpeter,imx53-ddc # K+P imx53 DDC
|
||||
- kiebackpeter,imx53-hsc # K+P imx53 HSC
|
||||
- menlo,m53menlo
|
||||
- menlo,m53menlo # i.MX53 Menlo board
|
||||
- voipac,imx53-dmm-668 # Voipac i.MX53 X53-DMM-668
|
||||
- const: fsl,imx53
|
||||
|
||||
|
|
@ -192,6 +192,7 @@ properties:
|
|||
items:
|
||||
- enum:
|
||||
- auvidea,h100 # Auvidea H100
|
||||
- bosch,imx6q-acc # Bosch ACC i.MX6 Dual
|
||||
- boundary,imx6q-nitrogen6_max
|
||||
- boundary,imx6q-nitrogen6_som2
|
||||
- boundary,imx6q-nitrogen6x
|
||||
|
|
@ -411,7 +412,6 @@ properties:
|
|||
- technologic,imx6dl-ts4900
|
||||
- technologic,imx6dl-ts7970
|
||||
- toradex,colibri_imx6dl # Colibri iMX6 Modules
|
||||
- toradex,colibri_imx6dl-v1_1 # Colibri iMX6 V1.1 Modules
|
||||
- udoo,imx6dl-udoo # Udoo i.MX6 Dual-lite Board
|
||||
- vdl,lanmcu # Van der Laan LANMCU board
|
||||
- wand,imx6dl-wandboard # Wandboard i.MX6 Dual Lite Board
|
||||
|
|
@ -488,17 +488,13 @@ properties:
|
|||
- description: i.MX6DL Boards with Toradex Colibri iMX6DL/S Modules
|
||||
items:
|
||||
- enum:
|
||||
- toradex,colibri_imx6dl-aster # Colibri iMX6DL/S Module on Aster Board
|
||||
- toradex,colibri_imx6dl-eval-v3 # Colibri iMX6DL/S Module on Colibri Evaluation Board V3
|
||||
- toradex,colibri_imx6dl-iris # Colibri iMX6DL/S Module on Iris Board
|
||||
- toradex,colibri_imx6dl-iris-v2 # Colibri iMX6DL/S Module on Iris Board V2
|
||||
- const: toradex,colibri_imx6dl # Colibri iMX6DL/S Module
|
||||
- const: fsl,imx6dl
|
||||
|
||||
- description: i.MX6DL Boards with Toradex Colibri iMX6DL/S V1.1 Modules
|
||||
items:
|
||||
- enum:
|
||||
- toradex,colibri_imx6dl-v1_1-eval-v3 # Colibri iMX6DL/S V1.1 M. on Colibri Evaluation Board V3
|
||||
- const: toradex,colibri_imx6dl-v1_1 # Colibri iMX6DL/S V1.1 Module
|
||||
- const: fsl,imx6dl
|
||||
|
||||
- description: i.MX6S DHCOM DRC02 Board
|
||||
items:
|
||||
- const: dh,imx6s-dhcom-drc02
|
||||
|
|
@ -613,6 +609,28 @@ properties:
|
|||
- const: kontron,imx6ul-n6310-som
|
||||
- const: fsl,imx6ul
|
||||
|
||||
- description: TQ-Systems TQMa6UL1 SoM on MBa6ULx board
|
||||
items:
|
||||
- enum:
|
||||
- tq,imx6ul-tqma6ul1-mba6ulx
|
||||
- const: tq,imx6ul-tqma6ul1 # MCIMX6G1
|
||||
- const: fsl,imx6ul
|
||||
|
||||
- description: TQ-Systems TQMa6UL2 SoM on MBa6ULx board
|
||||
items:
|
||||
- enum:
|
||||
- tq,imx6ul-tqma6ul2-mba6ulx
|
||||
- const: tq,imx6ul-tqma6ul2 # MCIMX6G2
|
||||
- const: fsl,imx6ul
|
||||
|
||||
- description: TQ-Systems TQMa6ULxL SoM on MBa6ULx[L] board
|
||||
items:
|
||||
- enum:
|
||||
- tq,imx6ul-tqma6ul2l-mba6ulx # using LGA adapter
|
||||
- tq,imx6ul-tqma6ul2l-mba6ulxl
|
||||
- const: tq,imx6ul-tqma6ul2l # MCIMX6G2, LGA SoM variant
|
||||
- const: fsl,imx6ul
|
||||
|
||||
- description: i.MX6ULL based Boards
|
||||
items:
|
||||
- enum:
|
||||
|
|
@ -640,26 +658,44 @@ properties:
|
|||
- const: phytec,imx6ull-pcl063 # PHYTEC phyCORE-i.MX 6ULL
|
||||
- const: fsl,imx6ull
|
||||
|
||||
- description: i.MX6ULL PHYTEC phyGATE-Tauri
|
||||
items:
|
||||
- enum:
|
||||
- phytec,imx6ull-phygate-tauri-emmc
|
||||
- phytec,imx6ull-phygate-tauri-nand
|
||||
- const: phytec,imx6ull-phygate-tauri # PHYTEC phyGATE-Tauri with i.MX6 ULL
|
||||
- const: phytec,imx6ull-pcl063 # PHYTEC phyCORE-i.MX 6ULL
|
||||
- const: fsl,imx6ull
|
||||
|
||||
- description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Modules
|
||||
items:
|
||||
- enum:
|
||||
- toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Evaluation Board
|
||||
- toradex,colibri-imx6ull-aster # Colibri iMX6ULL Module on Aster Carrier Board
|
||||
- toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Evaluation Board V3
|
||||
- toradex,colibri-imx6ull-iris # Colibri iMX6ULL Module on Iris Carrier Board
|
||||
- toradex,colibri-imx6ull-iris-v2 # Colibri iMX6ULL Module on Iris V2 Carrier Board
|
||||
- const: toradex,colibri-imx6ull # Colibri iMX6ULL Module
|
||||
- const: fsl,imx6dl
|
||||
- const: fsl,imx6ull
|
||||
|
||||
- description: i.MX6ULL Boards with Toradex Colibri iMX6ULL 1GB (eMMC) Module
|
||||
items:
|
||||
- enum:
|
||||
- toradex,colibri-imx6ull-emmc-eval # Colibri iMX6ULL 1GB (eMMC) M. on Colibri Evaluation Board
|
||||
- const: toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module
|
||||
- const: fsl,imx6dl
|
||||
- toradex,colibri-imx6ull-emmc-aster # Colibri iMX6ULL 1G (eMMC) on Aster Carrier Board
|
||||
- toradex,colibri-imx6ull-emmc-eval # Colibri iMX6ULL 1G (eMMC) on Colibri Evaluation B. V3
|
||||
- toradex,colibri-imx6ull-emmc-iris # Colibri iMX6ULL 1G (eMMC) on Iris Carrier Board
|
||||
- toradex,colibri-imx6ull-emmc-iris-v2 # Colibri iMX6ULL 1G (eMMC) on Iris V2 Carrier Board
|
||||
- const: toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module
|
||||
- const: fsl,imx6ull
|
||||
|
||||
- description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Wi-Fi / BT Modules
|
||||
items:
|
||||
- enum:
|
||||
- toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / BT M. on Colibri Evaluation Board
|
||||
- const: toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Module
|
||||
- const: fsl,imx6dl
|
||||
- toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / BT M. on Colibri Eval. B. V3
|
||||
- toradex,colibri-imx6ull-wifi-aster # Colibri iMX6ULL Wi-Fi / BT M. on Aster Carrier Board
|
||||
- toradex,colibri-imx6ull-wifi-iris # Colibri iMX6ULL Wi-Fi / BT M. on Iris Carrier Board
|
||||
- toradex,colibri-imx6ull-wifi-iris-v2 # Colibri iMX6ULL Wi-Fi / BT M. on Iris V2 Carrier Board
|
||||
- const: toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Module
|
||||
- const: fsl,imx6ull
|
||||
|
||||
- description: Kontron N6411 S Board
|
||||
items:
|
||||
|
|
@ -667,6 +703,21 @@ properties:
|
|||
- const: kontron,imx6ull-n6411-som
|
||||
- const: fsl,imx6ull
|
||||
|
||||
- description: TQ Systems TQMa6ULLx SoM on MBa6ULx board
|
||||
items:
|
||||
- enum:
|
||||
- tq,imx6ull-tqma6ull2-mba6ulx
|
||||
- const: tq,imx6ull-tqma6ull2 # MCIMX6Y2
|
||||
- const: fsl,imx6ull
|
||||
|
||||
- description: TQ Systems TQMa6ULLxL SoM on MBa6ULx[L] board
|
||||
items:
|
||||
- enum:
|
||||
- tq,imx6ull-tqma6ull2l-mba6ulx # using LGA adapter
|
||||
- tq,imx6ull-tqma6ull2l-mba6ulxl
|
||||
- const: tq,imx6ull-tqma6ull2l # MCIMX6Y2, LGA SoM variant
|
||||
- const: fsl,imx6ull
|
||||
|
||||
- description: i.MX6ULZ based Boards
|
||||
items:
|
||||
- enum:
|
||||
|
|
@ -707,6 +758,7 @@ properties:
|
|||
- kam,imx7d-flex-concentrator-mfg # Kamstrup OMNIA Flex Concentrator in manufacturing mode
|
||||
- novtech,imx7d-meerkat96 # i.MX7 Meerkat96 Board
|
||||
- remarkable,imx7d-remarkable2 # i.MX7D ReMarkable 2 E-Ink Tablet
|
||||
- storopack,imx7d-smegw01 # Storopack i.MX7D SMEGW01
|
||||
- technexion,imx7d-pico-dwarf # TechNexion i.MX7D Pico-Dwarf
|
||||
- technexion,imx7d-pico-hobbit # TechNexion i.MX7D Pico-Hobbit
|
||||
- technexion,imx7d-pico-nymph # TechNexion i.MX7D Pico-Nymph
|
||||
|
|
@ -762,6 +814,7 @@ properties:
|
|||
- enum:
|
||||
- beacon,imx8mm-beacon-kit # i.MX8MM Beacon Development Kit
|
||||
- boundary,imx8mm-nitrogen8mm # i.MX8MM Nitrogen Board
|
||||
- dmo,imx8mm-data-modul-edm-sbc # i.MX8MM eDM SBC
|
||||
- emtrion,emcon-mx8mm-avari # emCON-MX8MM SoM on Avari Base
|
||||
- fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board
|
||||
- fsl,imx8mm-evk # i.MX8MM EVK Board
|
||||
|
|
@ -772,6 +825,7 @@ properties:
|
|||
- gw,imx8mm-gw7902 # i.MX8MM Gateworks Board
|
||||
- gw,imx8mm-gw7903 # i.MX8MM Gateworks Board
|
||||
- kontron,imx8mm-n801x-som # i.MX8MM Kontron SL (N801X) SOM
|
||||
- menlo,mx8menlo # i.MX8MM Menlo board with Verdin SoM
|
||||
- toradex,verdin-imx8mm # Verdin iMX8M Mini Modules
|
||||
- toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Modules without Wi-Fi / BT
|
||||
- toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Modules
|
||||
|
|
@ -834,6 +888,7 @@ properties:
|
|||
- beacon,imx8mn-beacon-kit # i.MX8MN Beacon Development Kit
|
||||
- bsh,imx8mn-bsh-smm-s2 # i.MX8MN BSH SystemMaster S2
|
||||
- bsh,imx8mn-bsh-smm-s2pro # i.MX8MN BSH SystemMaster S2 PRO
|
||||
- fsl,imx8mn-ddr3l-evk # i.MX8MN DDR3L EVK Board
|
||||
- fsl,imx8mn-ddr4-evk # i.MX8MN DDR4 EVK Board
|
||||
- fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board
|
||||
- gw,imx8mn-gw7902 # i.MX8MM Gateworks Board
|
||||
|
|
@ -860,6 +915,17 @@ properties:
|
|||
items:
|
||||
- enum:
|
||||
- fsl,imx8mp-evk # i.MX8MP EVK Board
|
||||
- gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
|
||||
- toradex,verdin-imx8mp # Verdin iMX8M Plus Modules
|
||||
- toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT
|
||||
- toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules
|
||||
- const: fsl,imx8mp
|
||||
|
||||
- description: Engicam i.Core MX8M Plus SoM based boards
|
||||
items:
|
||||
- enum:
|
||||
- engicam,icore-mx8mp-edimm2.2 # i.MX8MP Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit
|
||||
- const: engicam,icore-mx8mp # i.MX8MP Engicam i.Core MX8M Plus SoM
|
||||
- const: fsl,imx8mp
|
||||
|
||||
- description: PHYTEC phyCORE-i.MX8MP SoM based boards
|
||||
|
|
@ -868,6 +934,24 @@ properties:
|
|||
- const: phytec,imx8mp-phycore-som # phyCORE-i.MX8MP SoM
|
||||
- const: fsl,imx8mp
|
||||
|
||||
- description: Toradex Boards with Verdin iMX8M Plus Modules
|
||||
items:
|
||||
- enum:
|
||||
- toradex,verdin-imx8mp-nonwifi-dahlia # Verdin iMX8M Plus Module on Dahlia
|
||||
- toradex,verdin-imx8mp-nonwifi-dev # Verdin iMX8M Plus Module on Verdin Development Board
|
||||
- const: toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Module without Wi-Fi / BT
|
||||
- const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module
|
||||
- const: fsl,imx8mp
|
||||
|
||||
- description: Toradex Boards with Verdin iMX8M Plus Wi-Fi / BT Modules
|
||||
items:
|
||||
- enum:
|
||||
- toradex,verdin-imx8mp-wifi-dahlia # Verdin iMX8M Plus Wi-Fi / BT Module on Dahlia
|
||||
- toradex,verdin-imx8mp-wifi-dev # Verdin iMX8M Plus Wi-Fi / BT M. on Verdin Development B.
|
||||
- const: toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Module
|
||||
- const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module
|
||||
- const: fsl,imx8mp
|
||||
|
||||
- description: i.MX8MQ based Boards
|
||||
items:
|
||||
- enum:
|
||||
|
|
@ -999,6 +1083,7 @@ properties:
|
|||
- description: LS1021A based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,ls1021a-iot
|
||||
- fsl,ls1021a-moxa-uc-8410a
|
||||
- fsl,ls1021a-qds
|
||||
- fsl,ls1021a-tsn
|
||||
|
|
|
|||
|
|
@ -133,6 +133,11 @@ properties:
|
|||
- const: mediatek,mt8183
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8192-evb
|
||||
- const: mediatek,mt8192
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8195-demo
|
||||
- mediatek,mt8195-evb
|
||||
- const: mediatek,mt8195
|
||||
- description: Google Burnet (HP Chromebook x360 11MK G3 EE)
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@ properties:
|
|||
- mediatek,mt8135-pericfg
|
||||
- mediatek,mt8173-pericfg
|
||||
- mediatek,mt8183-pericfg
|
||||
- mediatek,mt8195-pericfg
|
||||
- mediatek,mt8516-pericfg
|
||||
- const: syscon
|
||||
- items:
|
||||
|
|
|
|||
|
|
@ -31,12 +31,17 @@ Required properties:
|
|||
(base address and length)
|
||||
- clocks: clocks for this module
|
||||
- clockdomains: clockdomains for this module
|
||||
- #clock-cells: From common clock binding
|
||||
- clock-output-names: From common clock binding
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
cm: cm@48004000 {
|
||||
cm: clock@48004000 {
|
||||
compatible = "ti,omap3-cm";
|
||||
reg = <0x48004000 0x4000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "cm";
|
||||
|
||||
cm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -99,6 +99,7 @@ properties:
|
|||
|
||||
- items:
|
||||
- enum:
|
||||
- asus,sparrow
|
||||
- lg,lenok
|
||||
- const: qcom,apq8026
|
||||
|
||||
|
|
|
|||
|
|
@ -327,6 +327,18 @@ properties:
|
|||
- const: renesas,spider-cpu
|
||||
- const: renesas,r8a779f0
|
||||
|
||||
- description: R-Car V4H (R8A779G0)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,white-hawk-cpu # White Hawk CPU board (RTP8A779G0ASKB0FC0SA000)
|
||||
- const: renesas,r8a779g0
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,white-hawk-breakout # White Hawk BreakOut board (RTP8A779G0ASKB0SB0SA000)
|
||||
- const: renesas,white-hawk-cpu
|
||||
- const: renesas,r8a779g0
|
||||
|
||||
- description: R-Car H3e (R8A779M0)
|
||||
items:
|
||||
- enum:
|
||||
|
|
@ -405,6 +417,8 @@ properties:
|
|||
|
||||
- description: RZ/G2UL (R9A07G043)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,smarc-evk # SMARC EVK
|
||||
- enum:
|
||||
- renesas,r9a07g043u11 # RZ/G2UL Type-1
|
||||
- renesas,r9a07g043u12 # RZ/G2UL Type-2
|
||||
|
|
@ -430,6 +444,12 @@ properties:
|
|||
- renesas,r9a07g054l2 # Dual Cortex-A55 RZ/V2L
|
||||
- const: renesas,r9a07g054
|
||||
|
||||
- description: RZ/V2M (R9A09G011)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,rzv2mevk2 # RZ/V2M Eval Board v2.0
|
||||
- const: renesas,r9a09g011
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
|
|
|
|||
|
|
@ -133,6 +133,11 @@ properties:
|
|||
- firefly,roc-rk3399-pc-plus
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Firefly Station M2
|
||||
items:
|
||||
- const: firefly,rk3566-roc-pc
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: FriendlyElec NanoPi R2S
|
||||
items:
|
||||
- const: friendlyarm,nanopi-r2s
|
||||
|
|
@ -502,9 +507,18 @@ properties:
|
|||
- const: pine64,rockpro64
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Pine64 Quartz64 Model A
|
||||
- description: Pine64 Quartz64 Model A/B
|
||||
items:
|
||||
- const: pine64,quartz64-a
|
||||
- enum:
|
||||
- pine64,quartz64-a
|
||||
- pine64,quartz64-b
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: Pine64 SoQuartz SoM
|
||||
items:
|
||||
- enum:
|
||||
- pine64,soquartz-cm4io
|
||||
- const: pine64,soquartz
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: Radxa Rock
|
||||
|
|
@ -545,6 +559,11 @@ properties:
|
|||
- const: radxa,rock2-square
|
||||
- const: rockchip,rk3288
|
||||
|
||||
- description: Radxa ROCK3 Model A
|
||||
items:
|
||||
- const: radxa,rock3a
|
||||
- const: rockchip,rk3568
|
||||
|
||||
- description: Rikomagic MK808 v1
|
||||
items:
|
||||
- const: rikomagic,mk808
|
||||
|
|
|
|||
|
|
@ -14,21 +14,6 @@ properties:
|
|||
const: "/"
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: DH STM32MP1 SoM based Boards
|
||||
items:
|
||||
- enum:
|
||||
- arrow,stm32mp157a-avenger96 # Avenger96
|
||||
- dh,stm32mp153c-dhcom-drc02
|
||||
- dh,stm32mp157c-dhcom-pdk2
|
||||
- dh,stm32mp157c-dhcom-picoitx
|
||||
- enum:
|
||||
- dh,stm32mp153c-dhcom-som
|
||||
- dh,stm32mp157a-dhcor-som
|
||||
- dh,stm32mp157c-dhcom-som
|
||||
- enum:
|
||||
- st,stm32mp153
|
||||
- st,stm32mp157
|
||||
|
||||
- description: emtrion STM32MP1 Argon based Boards
|
||||
items:
|
||||
- const: emtrion,stm32mp157c-emsbc-argon
|
||||
|
|
@ -65,6 +50,21 @@ properties:
|
|||
- enum:
|
||||
- st,stm32mp135f-dk
|
||||
- const: st,stm32mp135
|
||||
|
||||
- description: ST STM32MP151 based Boards
|
||||
items:
|
||||
- enum:
|
||||
- prt,prtt1a # Protonic PRTT1A
|
||||
- prt,prtt1c # Protonic PRTT1C
|
||||
- prt,prtt1s # Protonic PRTT1S
|
||||
- const: st,stm32mp151
|
||||
|
||||
- description: DH STM32MP153 SoM based Boards
|
||||
items:
|
||||
- const: dh,stm32mp153c-dhcom-drc02
|
||||
- const: dh,stm32mp153c-dhcom-som
|
||||
- const: st,stm32mp153
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- shiratech,stm32mp157a-iot-box # IoT Box
|
||||
|
|
@ -72,12 +72,44 @@ properties:
|
|||
- st,stm32mp157c-ed1
|
||||
- st,stm32mp157a-dk1
|
||||
- st,stm32mp157c-dk2
|
||||
- const: st,stm32mp157
|
||||
|
||||
- items:
|
||||
- const: st,stm32mp157a-dk1-scmi
|
||||
- const: st,stm32mp157a-dk1
|
||||
- const: st,stm32mp157
|
||||
- items:
|
||||
- const: st,stm32mp157c-dk2-scmi
|
||||
- const: st,stm32mp157c-dk2
|
||||
- const: st,stm32mp157
|
||||
- items:
|
||||
- const: st,stm32mp157c-ed1-scmi
|
||||
- const: st,stm32mp157c-ed1
|
||||
- const: st,stm32mp157
|
||||
- items:
|
||||
- const: st,stm32mp157c-ev1
|
||||
- const: st,stm32mp157c-ed1
|
||||
- const: st,stm32mp157
|
||||
- items:
|
||||
- const: st,stm32mp157c-ev1-scmi
|
||||
- const: st,stm32mp157c-ev1
|
||||
- const: st,stm32mp157c-ed1
|
||||
- const: st,stm32mp157
|
||||
|
||||
- description: DH STM32MP1 SoM based Boards
|
||||
items:
|
||||
- enum:
|
||||
- arrow,stm32mp157a-avenger96 # Avenger96
|
||||
- const: dh,stm32mp157a-dhcor-som
|
||||
- const: st,stm32mp157
|
||||
|
||||
- description: DH STM32MP1 SoM based Boards
|
||||
items:
|
||||
- enum:
|
||||
- dh,stm32mp157c-dhcom-pdk2
|
||||
- dh,stm32mp157c-dhcom-picoitx
|
||||
- const: dh,stm32mp157c-dhcom-som
|
||||
- const: st,stm32mp157
|
||||
|
||||
- description: Engicam i.Core STM32MP1 SoM based Boards
|
||||
items:
|
||||
|
|
@ -103,6 +135,7 @@ properties:
|
|||
- const: oct,stm32mp15xx-osd32
|
||||
- enum:
|
||||
- st,stm32mp157
|
||||
|
||||
- description: Odyssey STM32MP1 SoM based Boards
|
||||
items:
|
||||
- enum:
|
||||
|
|
|
|||
|
|
@ -391,6 +391,11 @@ properties:
|
|||
- const: libretech,all-h5-cc-h5
|
||||
- const: allwinner,sun50i-h5
|
||||
|
||||
- description: Lichee Pi Nano
|
||||
items:
|
||||
- const: licheepi,licheepi-nano
|
||||
- const: allwinner,suniv-f1c100s
|
||||
|
||||
- description: Lichee Pi One
|
||||
items:
|
||||
- const: licheepi,licheepi-one
|
||||
|
|
|
|||
|
|
@ -18,10 +18,6 @@ stable binding/ABI.
|
|||
|
||||
---------------------------------------------------------------
|
||||
|
||||
Boards with the Synaptics AS370 SoC shall have the following properties:
|
||||
Required root node property:
|
||||
compatible: "syna,as370"
|
||||
|
||||
Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
|
||||
shall have the following properties:
|
||||
|
||||
|
|
|
|||
|
|
@ -40,6 +40,11 @@ properties:
|
|||
- const: samsung,codina
|
||||
- const: st-ericsson,u8500
|
||||
|
||||
- description: Samsung Galaxy Exhibit (SGH-T599)
|
||||
items:
|
||||
- const: samsung,codina-tmo
|
||||
- const: st-ericsson,u8500
|
||||
|
||||
- description: Samsung Galaxy Beam (GT-I8530)
|
||||
items:
|
||||
- const: samsung,gavini
|
||||
|
|
|
|||
|
|
@ -0,0 +1,172 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sc7280-lpasscorecc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm LPASS Core & Audio Clock Controller Binding for SC7280
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm LPASS core and audio clock control module which supports the
|
||||
clocks and power domains on SC7280.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,lpasscorecc-sc7280.h
|
||||
- dt-bindings/clock/qcom,lpassaudiocc-sc7280.h
|
||||
|
||||
properties:
|
||||
clocks: true
|
||||
|
||||
clock-names: true
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sc7280-lpassaoncc
|
||||
- qcom,sc7280-lpassaudiocc
|
||||
- qcom,sc7280-lpasscorecc
|
||||
- qcom,sc7280-lpasshm
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: qcom,sc7280-lpassaudiocc
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: LPASS_AON_CC_MAIN_RCG_CLK_SRC
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: lpass_aon_cc_main_rcg_clk_src
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sc7280-lpassaoncc
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board XO active only source
|
||||
- description: LPASS_AON_CC_MAIN_RCG_CLK_SRC
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: bi_tcxo_ao
|
||||
- const: iface
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sc7280-lpasshm
|
||||
- qcom,sc7280-lpasscorecc
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
|
||||
#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
|
||||
#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
|
||||
lpass_audiocc: clock-controller@3300000 {
|
||||
compatible = "qcom,sc7280-lpassaudiocc";
|
||||
reg = <0x3300000 0x30000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>;
|
||||
clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
|
||||
power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
|
||||
#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
|
||||
#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
|
||||
lpass_hm: clock-controller@3c00000 {
|
||||
compatible = "qcom,sc7280-lpasshm";
|
||||
reg = <0x3c00000 0x28>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "bi_tcxo";
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
|
||||
#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
|
||||
#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
|
||||
lpasscore: clock-controller@3900000 {
|
||||
compatible = "qcom,sc7280-lpasscorecc";
|
||||
reg = <0x3900000 0x50000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "bi_tcxo";
|
||||
power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>;
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
|
||||
#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
|
||||
#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
|
||||
lpass_aon: clock-controller@3380000 {
|
||||
compatible = "qcom,sc7280-lpassaoncc";
|
||||
reg = <0x3380000 0x30000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&lpasscore LPASS_CORE_CC_CORE_CLK>;
|
||||
clock-names = "bi_tcxo", "bi_tcxo_ao","iface";
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -0,0 +1,219 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/samsung,exynosautov9-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos Auto v9 SoC clock controller
|
||||
|
||||
maintainers:
|
||||
- Chanho Park <chanho61.park@samsung.com>
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
- Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
- Tomasz Figa <tomasz.figa@gmail.com>
|
||||
|
||||
description: |
|
||||
Exynos Auto v9 clock controller is comprised of several CMU units, generating
|
||||
clocks for different domains. Those CMU units are modeled as separate device
|
||||
tree nodes, and might depend on each other. Root clocks in that clock tree are
|
||||
two external clocks:: OSCCLK/XTCXO (26 MHz) and RTCCLK/XrtcXTI (32768 Hz).
|
||||
The external OSCCLK must be defined as fixed-rate clock in dts.
|
||||
|
||||
CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
|
||||
dividers; all other clocks of function blocks (other CMUs) are usually
|
||||
derived from CMU_TOP.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All clocks available for usage
|
||||
in clock consumer nodes are defined as preprocessor macros in
|
||||
'include/dt-bindings/clock/samsung,exynosautov9.h' header.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynosautov9-cmu-top
|
||||
- samsung,exynosautov9-cmu-busmc
|
||||
- samsung,exynosautov9-cmu-core
|
||||
- samsung,exynosautov9-cmu-fsys2
|
||||
- samsung,exynosautov9-cmu-peric0
|
||||
- samsung,exynosautov9-cmu-peric1
|
||||
- samsung,exynosautov9-cmu-peris
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 5
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 5
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynosautov9-cmu-top
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynosautov9-cmu-busmc
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_BUSMC bus clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: dout_clkcmu_busmc_bus
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynosautov9-cmu-core
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_CORE bus clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: dout_clkcmu_core_bus
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynosautov9-cmu-fsys2
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_FSYS2 bus clock (from CMU_TOP)
|
||||
- description: UFS clock (from CMU_TOP)
|
||||
- description: Ethernet clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: dout_clkcmu_fsys2_bus
|
||||
- const: dout_fsys2_clkcmu_ufs_embd
|
||||
- const: dout_fsys2_clkcmu_ethernet
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynosautov9-cmu-peric0
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_PERIC0 bus clock (from CMU_TOP)
|
||||
- description: PERIC0 IP clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: dout_clkcmu_peric0_bus
|
||||
- const: dout_clkcmu_peric0_ip
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynosautov9-cmu-peric1
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_PERIC1 bus clock (from CMU_TOP)
|
||||
- description: PERIC1 IP clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: dout_clkcmu_peric1_bus
|
||||
- const: dout_clkcmu_peric1_ip
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynosautov9-cmu-peris
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_PERIS bus clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: dout_clkcmu_peris_bus
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Clock controller node for CMU_FSYS2
|
||||
- |
|
||||
#include <dt-bindings/clock/samsung,exynosautov9.h>
|
||||
|
||||
cmu_fsys2: clock-controller@17c00000 {
|
||||
compatible = "samsung,exynosautov9-cmu-fsys2";
|
||||
reg = <0x17c00000 0x8000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&xtcxo>,
|
||||
<&cmu_top DOUT_CLKCMU_FSYS2_BUS>,
|
||||
<&cmu_top DOUT_CLKCMU_FSYS2_UFS_EMBD>,
|
||||
<&cmu_top DOUT_CLKCMU_FSYS2_ETHERNET>;
|
||||
clock-names = "oscclk",
|
||||
"dout_clkcmu_fsys2_bus",
|
||||
"dout_fsys2_clkcmu_ufs_embd",
|
||||
"dout_fsys2_clkcmu_ethernet";
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -58,6 +58,8 @@ properties:
|
|||
- st,stm32mp1-rcc-secure
|
||||
- st,stm32mp1-rcc
|
||||
- const: syscon
|
||||
clocks: true
|
||||
clock-names: true
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
@ -68,14 +70,53 @@ required:
|
|||
- compatible
|
||||
- reg
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- st,stm32mp1-rcc-secure
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
description: Specifies oscillators.
|
||||
maxItems: 5
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: hse
|
||||
- const: hsi
|
||||
- const: csi
|
||||
- const: lse
|
||||
- const: lsi
|
||||
required:
|
||||
- clocks
|
||||
- clock-names
|
||||
else:
|
||||
properties:
|
||||
clocks:
|
||||
description:
|
||||
Specifies the external RX clock for ethernet MAC.
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: ETH_RX_CLK/ETH_REF_CLK
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/stm32mp1-clks.h>
|
||||
rcc: rcc@50000000 {
|
||||
compatible = "st,stm32mp1-rcc-secure", "syscon";
|
||||
reg = <0x50000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
clock-names = "hse", "hsi", "csi", "lse", "lsi";
|
||||
clocks = <&scmi_clk CK_SCMI_HSE>,
|
||||
<&scmi_clk CK_SCMI_HSI>,
|
||||
<&scmi_clk CK_SCMI_CSI>,
|
||||
<&scmi_clk CK_SCMI_LSE>,
|
||||
<&scmi_clk CK_SCMI_LSI>;
|
||||
};
|
||||
...
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@ Required properties :
|
|||
"ti,clkctrl-l4-per"
|
||||
"ti,clkctrl-l4-secure"
|
||||
"ti,clkctrl-l4-wkup"
|
||||
- clock-output-names : from common clock binding
|
||||
- #clock-cells : shall contain 2 with the first entry being the instance
|
||||
offset from the clock domain base and the second being the
|
||||
clock index
|
||||
|
|
@ -32,7 +33,8 @@ Example: Clock controller node on omap 4430:
|
|||
l4per: cm@1400 {
|
||||
cm_l4per@0 {
|
||||
cm_l4per_clkctrl: clock@20 {
|
||||
compatible = "ti,clkctrl-l4-per", "ti,clkctrl";
|
||||
compatible = "ti,clkctrl";
|
||||
clock-output-names = "l4_per";
|
||||
reg = <0x20 0x1b0>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -17,6 +17,9 @@ Required properties:
|
|||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clocks : link phandles of clocks within this domain
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names : from common clock binding.
|
||||
|
||||
Examples:
|
||||
dss_clkdm: dss_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
|
|
|
|||
|
|
@ -27,6 +27,9 @@ Required properties:
|
|||
- clocks : link phandles of component clocks
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names : from common clock binding.
|
||||
|
||||
Examples:
|
||||
|
||||
usb_l4_gate_ick: usb_l4_gate_ick {
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@ Required properties:
|
|||
- clocks: parent clock.
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names : from common clock binding.
|
||||
- ti,autoidle-shift: bit shift of the autoidle enable bit for the clock,
|
||||
see [2]
|
||||
- reg: offset for the autoidle register of this clock, see [2]
|
||||
|
|
|
|||
|
|
@ -36,6 +36,7 @@ Required properties:
|
|||
ti,clkdm-gate-clock type
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names : from common clock binding.
|
||||
- ti,bit-shift : bit shift for programming the clock gate, invalid for
|
||||
ti,clkdm-gate-clock type
|
||||
- ti,set-bit-to-disable : inverts default gate programming. Setting the bit
|
||||
|
|
|
|||
|
|
@ -28,6 +28,7 @@ Required properties:
|
|||
- reg : base address for the control register
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names : from common clock binding.
|
||||
- ti,bit-shift : bit shift for the bit enabling/disabling the clock (default 0)
|
||||
|
||||
Examples:
|
||||
|
|
|
|||
|
|
@ -42,6 +42,7 @@ Required properties:
|
|||
- reg : register offset for register controlling adjustable mux
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names : from common clock binding.
|
||||
- ti,bit-shift : number of bits to shift the bit-mask, defaults to
|
||||
0 if not present
|
||||
- ti,index-starts-at-one : valid input select programming starts at 1, not
|
||||
|
|
|
|||
|
|
@ -13,8 +13,10 @@ Required properties:
|
|||
- #dma-cells : Has to be 1. imx-dma does not support anything else.
|
||||
|
||||
Optional properties:
|
||||
- #dma-channels : Number of DMA channels supported. Should be 16.
|
||||
- #dma-requests : Number of DMA requests supported.
|
||||
- dma-channels : Number of DMA channels supported. Should be 16.
|
||||
- #dma-channels : deprecated
|
||||
- dma-requests : Number of DMA requests supported.
|
||||
- #dma-requests : deprecated
|
||||
|
||||
Example:
|
||||
|
||||
|
|
@ -23,7 +25,7 @@ Example:
|
|||
reg = <0x10001000 0x1000>;
|
||||
interrupts = <32 33>;
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <16>;
|
||||
dma-channels = <16>;
|
||||
};
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -34,8 +34,12 @@ properties:
|
|||
- nvidia,tegra234-mc
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
minItems: 6
|
||||
maxItems: 18
|
||||
|
||||
reg-names:
|
||||
minItems: 6
|
||||
maxItems: 18
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
|
|
@ -142,7 +146,18 @@ allOf:
|
|||
then:
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
maxItems: 6
|
||||
description: 5 memory controller channels and 1 for stream-id registers
|
||||
|
||||
reg-names:
|
||||
maxItems: 6
|
||||
items:
|
||||
- const: sid
|
||||
- const: broadcast
|
||||
- const: ch0
|
||||
- const: ch1
|
||||
- const: ch2
|
||||
- const: ch3
|
||||
|
||||
- if:
|
||||
properties:
|
||||
|
|
@ -151,7 +166,30 @@ allOf:
|
|||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 3
|
||||
minItems: 18
|
||||
description: 17 memory controller channels and 1 for stream-id registers
|
||||
|
||||
reg-names:
|
||||
minItems: 18
|
||||
items:
|
||||
- const: sid
|
||||
- const: broadcast
|
||||
- const: ch0
|
||||
- const: ch1
|
||||
- const: ch2
|
||||
- const: ch3
|
||||
- const: ch4
|
||||
- const: ch5
|
||||
- const: ch6
|
||||
- const: ch7
|
||||
- const: ch8
|
||||
- const: ch9
|
||||
- const: ch10
|
||||
- const: ch11
|
||||
- const: ch12
|
||||
- const: ch13
|
||||
- const: ch14
|
||||
- const: ch15
|
||||
|
||||
- if:
|
||||
properties:
|
||||
|
|
@ -160,13 +198,37 @@ allOf:
|
|||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 3
|
||||
minItems: 18
|
||||
description: 17 memory controller channels and 1 for stream-id registers
|
||||
|
||||
reg-names:
|
||||
minItems: 18
|
||||
items:
|
||||
- const: sid
|
||||
- const: broadcast
|
||||
- const: ch0
|
||||
- const: ch1
|
||||
- const: ch2
|
||||
- const: ch3
|
||||
- const: ch4
|
||||
- const: ch5
|
||||
- const: ch6
|
||||
- const: ch7
|
||||
- const: ch8
|
||||
- const: ch9
|
||||
- const: ch10
|
||||
- const: ch11
|
||||
- const: ch12
|
||||
- const: ch13
|
||||
- const: ch14
|
||||
- const: ch15
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- interrupts
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
|
|
@ -182,7 +244,13 @@ examples:
|
|||
|
||||
memory-controller@2c00000 {
|
||||
compatible = "nvidia,tegra186-mc";
|
||||
reg = <0x0 0x02c00000 0x0 0xb0000>;
|
||||
reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
|
||||
<0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */
|
||||
<0x0 0x02c20000 0x0 0x10000>, /* MC0 */
|
||||
<0x0 0x02c30000 0x0 0x10000>, /* MC1 */
|
||||
<0x0 0x02c40000 0x0 0x10000>, /* MC2 */
|
||||
<0x0 0x02c50000 0x0 0x10000>; /* MC3 */
|
||||
reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3";
|
||||
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
#address-cells = <2>;
|
||||
|
|
|
|||
|
|
@ -39,6 +39,7 @@ properties:
|
|||
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,r9a07g043-rpc-if # RZ/G2UL
|
||||
- renesas,r9a07g044-rpc-if # RZ/G2{L,LC}
|
||||
- renesas,r9a07g054-rpc-if # RZ/V2L
|
||||
- const: renesas,rzg2l-rpc-if
|
||||
|
|
|
|||
|
|
@ -39,6 +39,7 @@ properties:
|
|||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- prt,prtt1c-wfm200 # Protonic PRTT1C Board
|
||||
- silabs,brd4001a # WGM160P Evaluation Board
|
||||
- silabs,brd8022a # WF200 Evaluation Board
|
||||
- silabs,brd8023a # WFM200 Evaluation Board
|
||||
|
|
|
|||
|
|
@ -44,6 +44,7 @@ properties:
|
|||
- renesas,r8a77995-sysc # R-Car D3
|
||||
- renesas,r8a779a0-sysc # R-Car V3U
|
||||
- renesas,r8a779f0-sysc # R-Car S4-8
|
||||
- renesas,r8a779g0-sysc # R-Car V4H
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
|
|||
|
|
@ -49,6 +49,7 @@ properties:
|
|||
- renesas,r8a77995-rst # R-Car D3
|
||||
- renesas,r8a779a0-rst # R-Car V3U
|
||||
- renesas,r8a779f0-rst # R-Car S4-8
|
||||
- renesas,r8a779g0-rst # R-Car V4H
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
|
|||
|
|
@ -0,0 +1,84 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NXP i.MX8MP HDMI blk-ctrl
|
||||
|
||||
maintainers:
|
||||
- Lucas Stach <l.stach@pengutronix.de>
|
||||
|
||||
description:
|
||||
The i.MX8MP HDMMI blk-ctrl is a top-level peripheral providing access to
|
||||
the NoC and ensuring proper power sequencing of the display pipeline
|
||||
peripherals located in the HDMI domain of the SoC.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: fsl,imx8mp-hdmi-blk-ctrl
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
power-domains:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
|
||||
power-domain-names:
|
||||
items:
|
||||
- const: bus
|
||||
- const: irqsteer
|
||||
- const: lcdif
|
||||
- const: pai
|
||||
- const: pvi
|
||||
- const: trng
|
||||
- const: hdmi-tx
|
||||
- const: hdmi-tx-phy
|
||||
|
||||
clocks:
|
||||
minItems: 4
|
||||
maxItems: 4
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: apb
|
||||
- const: axi
|
||||
- const: ref_266m
|
||||
- const: ref_24m
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- power-domains
|
||||
- power-domain-names
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/imx8mp-clock.h>
|
||||
#include <dt-bindings/power/imx8mp-power.h>
|
||||
|
||||
blk-ctrl@32fc0000 {
|
||||
compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon";
|
||||
reg = <0x32fc0000 0x23c>;
|
||||
clocks = <&clk IMX8MP_CLK_HDMI_APB>,
|
||||
<&clk IMX8MP_CLK_HDMI_ROOT>,
|
||||
<&clk IMX8MP_CLK_HDMI_REF_266M>,
|
||||
<&clk IMX8MP_CLK_HDMI_24M>;
|
||||
clock-names = "apb", "axi", "ref_266m", "ref_24m";
|
||||
power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>, <&pgc_hdmimix>,
|
||||
<&pgc_hdmimix>, <&pgc_hdmimix>, <&pgc_hdmimix>,
|
||||
<&pgc_hdmimix>, <&pgc_hdmi_phy>;
|
||||
power-domain-names = "bus", "irqsteer", "lcdif", "pai", "pvi", "trng",
|
||||
"hdmi-tx", "hdmi-tx-phy";
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NXP i.MX8MP Media Block Control
|
||||
|
||||
maintainers:
|
||||
- Paul Elder <paul.elder@ideasonboard.com>
|
||||
|
||||
description:
|
||||
The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level peripheral
|
||||
providing access to the NoC and ensuring proper power sequencing of the
|
||||
peripherals within the MEDIAMIX domain.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: fsl,imx8mp-media-blk-ctrl
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 10
|
||||
|
||||
power-domain-names:
|
||||
items:
|
||||
- const: bus
|
||||
- const: mipi-dsi1
|
||||
- const: mipi-csi1
|
||||
- const: lcdif1
|
||||
- const: isi
|
||||
- const: mipi-csi2
|
||||
- const: lcdif2
|
||||
- const: isp
|
||||
- const: dwe
|
||||
- const: mipi-dsi2
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: The APB clock
|
||||
- description: The AXI clock
|
||||
- description: The pixel clock for the first CSI2 receiver (aclk)
|
||||
- description: The pixel clock for the second CSI2 receiver (aclk)
|
||||
- description: The pixel clock for the first LCDIF (pix_clk)
|
||||
- description: The pixel clock for the second LCDIF (pix_clk)
|
||||
- description: The core clock for the ISP (clk)
|
||||
- description: The MIPI-PHY reference clock used by DSI
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: apb
|
||||
- const: axi
|
||||
- const: cam1
|
||||
- const: cam2
|
||||
- const: disp1
|
||||
- const: disp2
|
||||
- const: isp
|
||||
- const: phy
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#power-domain-cells'
|
||||
- power-domains
|
||||
- power-domain-names
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/imx8mp-clock.h>
|
||||
#include <dt-bindings/power/imx8mp-power.h>
|
||||
|
||||
media_blk_ctl: blk-ctl@32ec0000 {
|
||||
compatible = "fsl,imx8mp-media-blk-ctrl", "syscon";
|
||||
reg = <0x32ec0000 0x138>;
|
||||
power-domains = <&mediamix_pd>, <&mipi_phy1_pd>, <&mipi_phy1_pd>,
|
||||
<&mediamix_pd>, <&mediamix_pd>, <&mipi_phy2_pd>,
|
||||
<&mediamix_pd>, <&ispdwp_pd>, <&ispdwp_pd>,
|
||||
<&mipi_phy2_pd>;
|
||||
power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", "lcdif1", "isi",
|
||||
"mipi-csi2", "lcdif2", "isp1", "dwe", "mipi-dsi2";
|
||||
clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
|
||||
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
|
||||
<&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
|
||||
<&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
|
||||
<&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
|
||||
<&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
|
||||
<&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
|
||||
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
|
||||
clock-names = "apb", "axi", "cam1", "cam2", "disp1", "disp2",
|
||||
"isp", "phy";
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/power/renesas,rzg2l-sysc.yaml#"
|
||||
$id: "http://devicetree.org/schemas/soc/renesas/renesas,rzg2l-sysc.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Renesas RZ/{G2L,V2L} System Controller (SYSC)
|
||||
|
|
@ -10,8 +10,8 @@ maintainers:
|
|||
- Geert Uytterhoeven <geert+renesas@glider.be>
|
||||
|
||||
description:
|
||||
The RZ/{G2L,V2L} System Controller (SYSC) performs system control of the LSI
|
||||
and supports following functions,
|
||||
The RZ/{G2L,V2L}-alike System Controller (SYSC) performs system control of
|
||||
the LSI and supports following functions,
|
||||
- External terminal state capture function
|
||||
- 34-bit address space access function
|
||||
- Low power consumption control
|
||||
|
|
@ -20,6 +20,7 @@ description:
|
|||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- renesas,r9a07g043-sysc # RZ/G2UL
|
||||
- renesas,r9a07g044-sysc # RZ/G2{L,LC}
|
||||
- renesas,r9a07g054-sysc # RZ/V2L
|
||||
|
||||
|
|
@ -26,6 +26,7 @@ properties:
|
|||
- allwinner,sun8i-r40-spi
|
||||
- allwinner,sun50i-h6-spi
|
||||
- allwinner,sun50i-h616-spi
|
||||
- allwinner,suniv-f1c100s-spi
|
||||
- const: allwinner,sun8i-h3-spi
|
||||
|
||||
reg:
|
||||
|
|
|
|||
|
|
@ -1201,6 +1201,8 @@ patternProperties:
|
|||
description: StorLink Semiconductors, Inc.
|
||||
"^storm,.*":
|
||||
description: Storm Semiconductor, Inc.
|
||||
"^storopack,.*":
|
||||
description: Storopack
|
||||
"^summit,.*":
|
||||
description: Summit microelectronics
|
||||
"^sunchip,.*":
|
||||
|
|
|
|||
|
|
@ -26,10 +26,8 @@ properties:
|
|||
- allwinner,sun50i-h616-wdt
|
||||
- allwinner,sun50i-r329-wdt
|
||||
- allwinner,sun50i-r329-wdt-reset
|
||||
- allwinner,suniv-f1c100s-wdt
|
||||
- const: allwinner,sun6i-a31-wdt
|
||||
- items:
|
||||
- const: allwinner,suniv-f1c100s-wdt
|
||||
- const: allwinner,sun4i-a10-wdt
|
||||
- const: allwinner,sun20i-d1-wdt
|
||||
- items:
|
||||
- const: allwinner,sun20i-d1-wdt-reset
|
||||
|
|
@ -41,14 +39,8 @@ properties:
|
|||
clocks:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: High-frequency oscillator input, divided internally
|
||||
- description: Low-frequency oscillator input, only found on some variants
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: hosc
|
||||
- const: losc
|
||||
- description: 32 KHz input clock
|
||||
- description: secondary clock source
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
|
@ -73,9 +65,14 @@ then:
|
|||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
items:
|
||||
- description: High-frequency oscillator input, divided internally
|
||||
- description: Low-frequency oscillator input
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
items:
|
||||
- const: hosc
|
||||
- const: losc
|
||||
|
||||
required:
|
||||
- clock-names
|
||||
|
|
@ -85,9 +82,6 @@ else:
|
|||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
maxItems: 1
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
|
|
|
|||
|
|
@ -103,6 +103,8 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
|
|||
bcm4708-asus-rt-ac56u.dtb \
|
||||
bcm4708-asus-rt-ac68u.dtb \
|
||||
bcm4708-buffalo-wzr-1750dhp.dtb \
|
||||
bcm4708-buffalo-wzr-1166dhp.dtb \
|
||||
bcm4708-buffalo-wzr-1166dhp2.dtb \
|
||||
bcm4708-linksys-ea6300-v1.dtb \
|
||||
bcm4708-linksys-ea6500-v2.dtb \
|
||||
bcm4708-luxul-xap-1510.dtb \
|
||||
|
|
@ -179,6 +181,8 @@ dtb-$(CONFIG_ARCH_BERLIN) += \
|
|||
berlin2q-marvell-dmp.dtb
|
||||
dtb-$(CONFIG_ARCH_BRCMSTB) += \
|
||||
bcm7445-bcm97445svmb.dtb
|
||||
dtb-$(CONFIG_ARCH_BCMBCA) += \
|
||||
bcm947622.dtb
|
||||
dtb-$(CONFIG_ARCH_CLPS711X) += \
|
||||
ep7211-edb7211.dtb
|
||||
dtb-$(CONFIG_ARCH_DAVINCI) += \
|
||||
|
|
@ -458,8 +462,10 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
|
|||
imx6dl-aristainetos_7.dtb \
|
||||
imx6dl-aristainetos2_4.dtb \
|
||||
imx6dl-aristainetos2_7.dtb \
|
||||
imx6dl-colibri-aster.dtb \
|
||||
imx6dl-colibri-eval-v3.dtb \
|
||||
imx6dl-colibri-v1_1-eval-v3.dtb \
|
||||
imx6dl-colibri-iris.dtb \
|
||||
imx6dl-colibri-iris-v2.dtb \
|
||||
imx6dl-cubox-i.dtb \
|
||||
imx6dl-cubox-i-emmc-som-v15.dtb \
|
||||
imx6dl-cubox-i-som-v15.dtb \
|
||||
|
|
@ -547,6 +553,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
|
|||
imx6q-b450v3.dtb \
|
||||
imx6q-b650v3.dtb \
|
||||
imx6q-b850v3.dtb \
|
||||
imx6q-bosch-acc.dtb \
|
||||
imx6q-cm-fx6.dtb \
|
||||
imx6q-cubox-i.dtb \
|
||||
imx6q-cubox-i-emmc-som-v15.dtb \
|
||||
|
|
@ -690,6 +697,9 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
|
|||
imx6ul-kontron-n6310-s.dtb \
|
||||
imx6ul-kontron-n6310-s-43.dtb \
|
||||
imx6ul-liteboard.dtb \
|
||||
imx6ul-tqma6ul1-mba6ulx.dtb \
|
||||
imx6ul-tqma6ul2-mba6ulx.dtb \
|
||||
imx6ul-tqma6ul2l-mba6ulx.dtb \
|
||||
imx6ul-opos6uldev.dtb \
|
||||
imx6ul-pico-dwarf.dtb \
|
||||
imx6ul-pico-hobbit.dtb \
|
||||
|
|
@ -701,15 +711,28 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
|
|||
imx6ul-tx6ul-0011.dtb \
|
||||
imx6ul-tx6ul-mainboard.dtb \
|
||||
imx6ull-14x14-evk.dtb \
|
||||
imx6ull-colibri-aster.dtb \
|
||||
imx6ull-colibri-emmc-aster.dtb \
|
||||
imx6ull-colibri-emmc-eval-v3.dtb \
|
||||
imx6ull-colibri-emmc-iris.dtb \
|
||||
imx6ull-colibri-emmc-iris-v2.dtb \
|
||||
imx6ull-colibri-eval-v3.dtb \
|
||||
imx6ull-colibri-iris.dtb \
|
||||
imx6ull-colibri-iris-v2.dtb \
|
||||
imx6ull-colibri-wifi-aster.dtb \
|
||||
imx6ull-colibri-wifi-eval-v3.dtb \
|
||||
imx6ull-colibri-wifi-iris.dtb \
|
||||
imx6ull-colibri-wifi-iris-v2.dtb \
|
||||
imx6ull-jozacp.dtb \
|
||||
imx6ull-myir-mys-6ulx-eval.dtb \
|
||||
imx6ull-opos6uldev.dtb \
|
||||
imx6ull-phytec-segin-ff-rdk-nand.dtb \
|
||||
imx6ull-phytec-segin-ff-rdk-emmc.dtb \
|
||||
imx6ull-phytec-segin-lc-rdk-nand.dtb \
|
||||
imx6ull-phytec-tauri-emmc.dtb \
|
||||
imx6ull-phytec-tauri-nand.dtb \
|
||||
imx6ull-tqma6ull2-mba6ulx.dtb \
|
||||
imx6ull-tqma6ull2l-mba6ulx.dtb \
|
||||
imx6ulz-14x14-evk.dtb \
|
||||
imx6ulz-bsh-smm-m2.dtb
|
||||
dtb-$(CONFIG_SOC_IMX7D) += \
|
||||
|
|
@ -732,6 +755,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \
|
|||
imx7d-sdb.dtb \
|
||||
imx7d-sdb-reva.dtb \
|
||||
imx7d-sdb-sht11.dtb \
|
||||
imx7d-smegw01.dtb \
|
||||
imx7d-zii-rmu2.dtb \
|
||||
imx7d-zii-rpu2.dtb \
|
||||
imx7s-colibri-aster.dtb \
|
||||
|
|
@ -741,9 +765,14 @@ dtb-$(CONFIG_SOC_IMX7D) += \
|
|||
dtb-$(CONFIG_SOC_IMX7ULP) += \
|
||||
imx7ulp-com.dtb \
|
||||
imx7ulp-evk.dtb
|
||||
dtb-$(CONFIG_SOC_IMXRT) += \
|
||||
imxrt1050-evk.dtb
|
||||
dtb-$(CONFIG_SOC_LAN966) += \
|
||||
lan966x-pcb8291.dtb
|
||||
lan966x-pcb8291.dtb \
|
||||
lan966x-kontron-kswitch-d10-mmt-6g-2gs.dtb \
|
||||
lan966x-kontron-kswitch-d10-mmt-8g.dtb
|
||||
dtb-$(CONFIG_SOC_LS1021A) += \
|
||||
ls1021a-iot.dtb \
|
||||
ls1021a-moxa-uc-8410a.dtb \
|
||||
ls1021a-qds.dtb \
|
||||
ls1021a-tsn.dtb \
|
||||
|
|
@ -977,11 +1006,12 @@ dtb-$(CONFIG_ARCH_OXNAS) += \
|
|||
ox820-cloudengines-pogoplug-series-3.dtb
|
||||
dtb-$(CONFIG_ARCH_QCOM) += \
|
||||
qcom-apq8016-sbc.dtb \
|
||||
qcom-apq8026-asus-sparrow.dtb \
|
||||
qcom-apq8026-lg-lenok.dtb \
|
||||
qcom-apq8060-dragonboard.dtb \
|
||||
qcom-apq8064-cm-qs600.dtb \
|
||||
qcom-apq8064-ifc6410.dtb \
|
||||
qcom-apq8064-sony-xperia-yuga.dtb \
|
||||
qcom-apq8064-sony-xperia-lagan-yuga.dtb \
|
||||
qcom-apq8064-asus-nexus7-flo.dtb \
|
||||
qcom-apq8074-dragonboard.dtb \
|
||||
qcom-apq8084-ifc6540.dtb \
|
||||
|
|
@ -1000,12 +1030,12 @@ dtb-$(CONFIG_ARCH_QCOM) += \
|
|||
qcom-msm8660-surf.dtb \
|
||||
qcom-msm8916-samsung-serranove.dtb \
|
||||
qcom-msm8960-cdp.dtb \
|
||||
qcom-msm8974-fairphone-fp2.dtb \
|
||||
qcom-msm8974-lge-nexus5-hammerhead.dtb \
|
||||
qcom-msm8974-samsung-klte.dtb \
|
||||
qcom-msm8974-sony-xperia-amami.dtb \
|
||||
qcom-msm8974-sony-xperia-castor.dtb \
|
||||
qcom-msm8974-sony-xperia-honami.dtb \
|
||||
qcom-msm8974-sony-xperia-rhine-amami.dtb \
|
||||
qcom-msm8974-sony-xperia-rhine-honami.dtb \
|
||||
qcom-msm8974pro-fairphone-fp2.dtb \
|
||||
qcom-msm8974pro-samsung-klte.dtb \
|
||||
qcom-msm8974pro-sony-xperia-shinano-castor.dtb \
|
||||
qcom-mdm9615-wp8548-mangoh-green.dtb \
|
||||
qcom-sdx55-mtp.dtb \
|
||||
qcom-sdx55-t55.dtb \
|
||||
|
|
@ -1156,10 +1186,14 @@ dtb-$(CONFIG_ARCH_STM32) += \
|
|||
stm32h743i-disco.dtb \
|
||||
stm32h750i-art-pi.dtb \
|
||||
stm32mp135f-dk.dtb \
|
||||
stm32mp151a-prtt1a.dtb \
|
||||
stm32mp151a-prtt1c.dtb \
|
||||
stm32mp151a-prtt1s.dtb \
|
||||
stm32mp153c-dhcom-drc02.dtb \
|
||||
stm32mp157a-avenger96.dtb \
|
||||
stm32mp157a-dhcor-avenger96.dtb \
|
||||
stm32mp157a-dk1.dtb \
|
||||
stm32mp157a-dk1-scmi.dtb \
|
||||
stm32mp157a-iot-box.dtb \
|
||||
stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \
|
||||
stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \
|
||||
|
|
@ -1170,9 +1204,12 @@ dtb-$(CONFIG_ARCH_STM32) += \
|
|||
stm32mp157c-dhcom-pdk2.dtb \
|
||||
stm32mp157c-dhcom-picoitx.dtb \
|
||||
stm32mp157c-dk2.dtb \
|
||||
stm32mp157c-dk2-scmi.dtb \
|
||||
stm32mp157c-ed1.dtb \
|
||||
stm32mp157c-ed1-scmi.dtb \
|
||||
stm32mp157c-emsbc-argon.dtb \
|
||||
stm32mp157c-ev1.dtb \
|
||||
stm32mp157c-ev1-scmi.dtb \
|
||||
stm32mp157c-lxa-mc1.dtb \
|
||||
stm32mp157c-odyssey.dtb
|
||||
dtb-$(CONFIG_MACH_SUN4I) += \
|
||||
|
|
@ -1382,6 +1419,7 @@ dtb-$(CONFIG_ARCH_U8500) += \
|
|||
ste-ux500-samsung-janice.dtb \
|
||||
ste-ux500-samsung-gavini.dtb \
|
||||
ste-ux500-samsung-codina.dtb \
|
||||
ste-ux500-samsung-codina-tmo.dtb \
|
||||
ste-ux500-samsung-skomer.dtb \
|
||||
ste-ux500-samsung-kyle.dtb
|
||||
dtb-$(CONFIG_ARCH_UNIPHIER) += \
|
||||
|
|
|
|||
|
|
@ -285,7 +285,7 @@
|
|||
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
|
||||
regulator-name = "vdd_mpu";
|
||||
regulator-min-microvolt = <912500>;
|
||||
regulator-max-microvolt = <1312500>;
|
||||
regulator-max-microvolt = <1351500>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -405,3 +405,7 @@
|
|||
&pruss_tm {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wkup_m3_ipc {
|
||||
firmware-name = "am335x-bone-scale-data.bin";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -782,3 +782,7 @@
|
|||
&pruss_tm {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wkup_m3_ipc {
|
||||
firmware-name = "am335x-evm-scale-data.bin";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -719,3 +719,7 @@
|
|||
&pruss_tm {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wkup_m3_ipc {
|
||||
firmware-name = "am335x-evm-scale-data.bin";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -29,39 +29,44 @@
|
|||
reg = <0x80000000 0x10000000>; /* 256 MB */
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
guardian_buttons: gpio-keys {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&guardian_button_pins>;
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gpio_keys_pins>;
|
||||
|
||||
button21 {
|
||||
select-button {
|
||||
label = "guardian-select-button";
|
||||
linux,code = <KEY_5>;
|
||||
gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
power-button {
|
||||
label = "guardian-power-button";
|
||||
linux,code = <KEY_POWER>;
|
||||
gpios = <&gpio2 21 0>;
|
||||
gpios = <&gpio2 21 GPIO_ACTIVE_LOW>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
guardian_leds: gpio-leds {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&leds_pins>;
|
||||
pinctrl-0 = <&guardian_led_pins>;
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led1 {
|
||||
label = "green:heartbeat";
|
||||
gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
|
||||
life-led {
|
||||
label = "guardian:life-led";
|
||||
gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
led2 {
|
||||
label = "green:mmc0";
|
||||
gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "mmc0";
|
||||
default-state = "off";
|
||||
};
|
||||
gpio-poweroff {
|
||||
compatible = "gpio-poweroff";
|
||||
gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
panel {
|
||||
|
|
@ -100,20 +105,36 @@
|
|||
|
||||
};
|
||||
|
||||
pwm7: dmtimer-pwm {
|
||||
guardian_beeper: dmtimer-pwm@7 {
|
||||
compatible = "ti,omap-dmtimer-pwm";
|
||||
ti,timers = <&timer7>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&dmtimer7_pins>;
|
||||
pinctrl-0 = <&guardian_beeper_pins>;
|
||||
ti,clock-source = <0x01>;
|
||||
};
|
||||
|
||||
vmmcsd_fixed: regulator-3v3 {
|
||||
vmmcsd_fixed: fixedregulator0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmmcsd_fixed";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
mt_keypad: mt_keypad@0 {
|
||||
compatible = "gpio-mt-keypad";
|
||||
debounce-delay-ms = <10>;
|
||||
col-scan-delay-us = <2>;
|
||||
keypad,num-lines = <5>;
|
||||
linux,no-autorepeat;
|
||||
gpio-activelow;
|
||||
line-gpios = <
|
||||
&gpio1 24 GPIO_ACTIVE_LOW /*gpio_56*/
|
||||
&gpio1 23 GPIO_ACTIVE_LOW /*gpio_55*/
|
||||
&gpio1 22 GPIO_ACTIVE_LOW /*gpio_54*/
|
||||
&gpio1 20 GPIO_ACTIVE_LOW /*gpio_52*/
|
||||
&gpio1 16 GPIO_ACTIVE_LOW /*gpio_48*/
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&elm {
|
||||
|
|
@ -133,28 +154,29 @@
|
|||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
|
||||
ti,nand-xfer-type = "prefetch-dma";
|
||||
ti,nand-ecc-opt = "bch16";
|
||||
ti,elm-id = <&elm>;
|
||||
nand-bus-width = <8>;
|
||||
gpmc,device-width = <1>;
|
||||
gpmc,sync-clk-ps = <0>;
|
||||
gpmc,cs-on-ns = <0>;
|
||||
gpmc,cs-rd-off-ns = <44>;
|
||||
gpmc,cs-wr-off-ns = <44>;
|
||||
gpmc,adv-on-ns = <6>;
|
||||
gpmc,adv-rd-off-ns = <34>;
|
||||
gpmc,adv-wr-off-ns = <44>;
|
||||
gpmc,cs-rd-off-ns = <30>;
|
||||
gpmc,cs-wr-off-ns = <30>;
|
||||
gpmc,adv-on-ns = <0>;
|
||||
gpmc,adv-rd-off-ns = <30>;
|
||||
gpmc,adv-wr-off-ns = <30>;
|
||||
gpmc,we-on-ns = <0>;
|
||||
gpmc,we-off-ns = <40>;
|
||||
gpmc,oe-on-ns = <0>;
|
||||
gpmc,oe-off-ns = <54>;
|
||||
gpmc,access-ns = <64>;
|
||||
gpmc,rd-cycle-ns = <82>;
|
||||
gpmc,wr-cycle-ns = <82>;
|
||||
gpmc,we-off-ns = <15>;
|
||||
gpmc,oe-on-ns = <1>;
|
||||
gpmc,oe-off-ns = <15>;
|
||||
gpmc,access-ns = <30>;
|
||||
gpmc,rd-cycle-ns = <30>;
|
||||
gpmc,wr-cycle-ns = <30>;
|
||||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wr-access-ns = <40>;
|
||||
gpmc,wr-access-ns = <0>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
|
||||
/*
|
||||
|
|
@ -198,18 +220,33 @@
|
|||
};
|
||||
|
||||
partition@6 {
|
||||
label = "u-boot-env";
|
||||
reg = <0x300000 0x40000>;
|
||||
label = "u-boot-2";
|
||||
reg = <0x300000 0x100000>;
|
||||
};
|
||||
|
||||
partition@7 {
|
||||
label = "u-boot-env.backup1";
|
||||
reg = <0x340000 0x40000>;
|
||||
label = "u-boot-2.backup1";
|
||||
reg = <0x400000 0x100000>;
|
||||
};
|
||||
|
||||
partition@8 {
|
||||
label = "u-boot-env";
|
||||
reg = <0x500000 0x40000>;
|
||||
};
|
||||
|
||||
partition@9 {
|
||||
label = "u-boot-env.backup1";
|
||||
reg = <0x540000 0x40000>;
|
||||
};
|
||||
|
||||
partition@10 {
|
||||
label = "splash-screen";
|
||||
reg = <0x580000 0x40000>;
|
||||
};
|
||||
|
||||
partition@11 {
|
||||
label = "UBI";
|
||||
reg = <0x380000 0x1fc80000>;
|
||||
reg = <0x5c0000 0x1fa40000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -228,6 +265,11 @@
|
|||
&lcdc {
|
||||
blue-and-red-wiring = "crossed";
|
||||
status = "okay";
|
||||
port {
|
||||
lcdc_0: endpoint@0 {
|
||||
remote-endpoint = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
|
|
@ -242,7 +284,6 @@
|
|||
&rtc {
|
||||
clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
|
||||
clock-names = "ext-clk", "int-clk";
|
||||
system-power-controller;
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
|
|
@ -255,14 +296,34 @@
|
|||
#include "tps65217.dtsi"
|
||||
|
||||
&tps {
|
||||
/*
|
||||
* Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only
|
||||
* mode") at poweroff. Most BeagleBone versions do not support RTC-only
|
||||
* mode and risk hardware damage if this mode is entered.
|
||||
*
|
||||
* For details, see linux-omap mailing list May 2015 thread
|
||||
* [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller
|
||||
* In particular, messages:
|
||||
* http://www.spinics.net/lists/linux-omap/msg118585.html
|
||||
* http://www.spinics.net/lists/linux-omap/msg118615.html
|
||||
*
|
||||
* You can override this later with
|
||||
* &tps { /delete-property/ ti,pmic-shutdown-controller; }
|
||||
* if you want to use RTC-only mode and made sure you are not affected
|
||||
* by the hardware problems. (Tip: double-check by performing a current
|
||||
* measurement after shutdown: it should be less than 1 mA.)
|
||||
*/
|
||||
ti,pmic-shutdown-controller;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <7>; /* NMI */
|
||||
|
||||
backlight {
|
||||
isel = <1>; /* 1 - ISET1, 2 ISET2 */
|
||||
fdim = <100>; /* TPS65217_BL_FDIM_100HZ */
|
||||
default-brightness = <100>;
|
||||
fdim = <500>; /* TPS65217_BL_FDIM_500HZ */
|
||||
default-brightness = <50>;
|
||||
/* 1(on) - enable current sink, while initialization */
|
||||
/* 0(off) - disable current sink, while initialization */
|
||||
isink-en = <1>;
|
||||
};
|
||||
|
||||
regulators {
|
||||
|
|
@ -272,6 +333,7 @@
|
|||
};
|
||||
|
||||
dcdc2_reg: regulator@1 {
|
||||
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
|
||||
regulator-name = "vdd_mpu";
|
||||
regulator-min-microvolt = <925000>;
|
||||
regulator-max-microvolt = <1351500>;
|
||||
|
|
@ -280,6 +342,7 @@
|
|||
};
|
||||
|
||||
dcdc3_reg: regulator@2 {
|
||||
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
|
||||
regulator-name = "vdd_core";
|
||||
regulator-min-microvolt = <925000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
|
|
@ -319,171 +382,364 @@
|
|||
};
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
gpio-line-names =
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"MirxWakeup",
|
||||
"",
|
||||
"";
|
||||
};
|
||||
|
||||
&gpio3 {
|
||||
ti,gpio-always-on;
|
||||
ti,no-reset-on-init;
|
||||
gpio-line-names =
|
||||
"",
|
||||
"MirxBtReset",
|
||||
"",
|
||||
"CcVolAdcEn",
|
||||
"MirxBlePause",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"AspEn",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"BatVolAdcEn",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
dr_mode = "peripheral";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
dr_mode = "host";
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
};
|
||||
|
||||
&am33xx_pinmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&clkout2_pin &gpio_pins>;
|
||||
pinctrl-0 = <&clkout2_pin &guardian_interface_pins>;
|
||||
|
||||
clkout2_pin: pinmux_clkout2_pin {
|
||||
pinctrl-single,pins = <
|
||||
/* xdma_event_intr1.clkout2 */
|
||||
AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3)
|
||||
>;
|
||||
};
|
||||
|
||||
dmtimer7_pins: pinmux_dmtimer7_pins {
|
||||
guardian_interface_pins: pinmux_interface_pins {
|
||||
pinctrl-single,pins = <
|
||||
AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE5)
|
||||
/* ADC_BATSENSE_EN */
|
||||
/* (A14) MCASP0_AHCLKx.gpio3[21] */
|
||||
AM33XX_IOPAD(0x9ac, PIN_OUTPUT_PULLDOWN | MUX_MODE7 )
|
||||
/* ADC_COINCELL_EN */
|
||||
/* (J16) MII1_TX_EN.gpio3[3] */
|
||||
AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE7 )
|
||||
/* ASP_ENABLE */
|
||||
/* (A13) MCASP0_ACLKx.gpio3[14] */
|
||||
AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLUP | MUX_MODE7)
|
||||
/* (D16) uart1_rxd.uart1_rxd */
|
||||
AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE7)
|
||||
/* (D15) uart1_txd.uart1_txd */
|
||||
AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE7)
|
||||
/*SWITCH-OFF_3V6*/
|
||||
/* (M18) gpio0[1] */
|
||||
AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE7)
|
||||
/* MIRACULIX */
|
||||
/* (H17) gmii1_crs.gpio3[1] */
|
||||
AM33XX_IOPAD(0x90c, PIN_OUTPUT_PULLDOWN | MUX_MODE7 )
|
||||
/* (H18) rmii1_refclk.gpio0[29] */
|
||||
AM33XX_IOPAD(0x944, PIN_OUTPUT_PULLDOWN | MUX_MODE7 )
|
||||
/* (J18) gmii1_txd3.gpio0[16] */
|
||||
AM33XX_IOPAD(0x91c, PIN_INPUT | MUX_MODE7 )
|
||||
/* (J17) gmii1_rxdv.gpio3[4] */
|
||||
AM33XX_IOPAD(0x918, PIN_OUTPUT_PULLDOWN | MUX_MODE7 )
|
||||
>;
|
||||
};
|
||||
|
||||
gpio_keys_pins: pinmux_gpio_keys_pins {
|
||||
guardian_beeper_pins: pinmux_dmtimer7_pins {
|
||||
pinctrl-single,pins = <
|
||||
AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE7)
|
||||
AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE5) /* (E18) timer7 */
|
||||
>;
|
||||
};
|
||||
|
||||
gpio_pins: pinmux_gpio_pins {
|
||||
guardian_button_pins: pinmux_guardian_button_pins {
|
||||
pinctrl-single,pins = <
|
||||
AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE7)
|
||||
AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE7)
|
||||
AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE7) /* (M16) gmii1_rxd0.gpio2[21] */
|
||||
AM33XX_IOPAD(0x884, PIN_INPUT | MUX_MODE7) /* (V9) gpmc_csn2.gpio1[31] */
|
||||
>;
|
||||
};
|
||||
|
||||
|
||||
i2c0_pins: pinmux_i2c0_pins {
|
||||
pinctrl-single,pins = <
|
||||
AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)
|
||||
AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)
|
||||
AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
|
||||
AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
|
||||
>;
|
||||
};
|
||||
|
||||
led_bl_pins: gpio_led_bl_pins {
|
||||
pinctrl-single,pins = <
|
||||
/* P9_14, gpmc_a[2].GPIO1[18] (backlight control) */
|
||||
AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
lcd_disen_pins: pinmux_lcd_disen_pins {
|
||||
pinctrl-single,pins = <
|
||||
/* P9_27, mcasp0_fsr.gpio3[19] (lcd_disen) */
|
||||
AM33XX_IOPAD(0x9a4, PIN_OUTPUT_PULLUP | SLEWCTRL_SLOW | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
lcd_pins_default: pinmux_lcd_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
/* (U10) gpmc_ad8.lcd_data23 */
|
||||
AM33XX_IOPAD(0x820, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
|
||||
/* (T10) gpmc_ad9.lcd_data22 */
|
||||
AM33XX_IOPAD(0x824, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
|
||||
/* (T11) gpmc_ad10.lcd_data21 */
|
||||
AM33XX_IOPAD(0x828, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
|
||||
/* (U12) gpmc_ad11.lcd_data20 */
|
||||
AM33XX_IOPAD(0x82c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
|
||||
/* (T12) gpmc_ad12.lcd_data19 */
|
||||
AM33XX_IOPAD(0x830, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
|
||||
/* (R12) gpmc_ad13.lcd_data18 */
|
||||
AM33XX_IOPAD(0x834, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
|
||||
/* (V13) gpmc_ad14.lcd_data17 */
|
||||
AM33XX_IOPAD(0x838, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
|
||||
/* (U13) gpmc_ad15.lcd_data16 */
|
||||
AM33XX_IOPAD(0x83c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
|
||||
/* lcd_data0.lcd_data0 */
|
||||
AM33XX_IOPAD(0x8a0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
|
||||
/* lcd_data1.lcd_data1 */
|
||||
AM33XX_IOPAD(0x8a4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
|
||||
/* lcd_data2.lcd_data2 */
|
||||
AM33XX_IOPAD(0x8a8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
|
||||
/* lcd_data3.lcd_data3 */
|
||||
AM33XX_IOPAD(0x8ac, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
|
||||
/* lcd_data4.lcd_data4 */
|
||||
AM33XX_IOPAD(0x8b0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
|
||||
/* lcd_data5.lcd_data5 */
|
||||
AM33XX_IOPAD(0x8b4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
|
||||
/* lcd_data6.lcd_data6 */
|
||||
AM33XX_IOPAD(0x8b8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
|
||||
/* lcd_data7.lcd_data7 */
|
||||
AM33XX_IOPAD(0x8bc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
|
||||
/* lcd_data8.lcd_data8 */
|
||||
AM33XX_IOPAD(0x8c0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
|
||||
/* lcd_data9.lcd_data9 */
|
||||
AM33XX_IOPAD(0x8c4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
|
||||
/* lcd_data10.lcd_data10 */
|
||||
AM33XX_IOPAD(0x8c8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
|
||||
/* lcd_data11.lcd_data11 */
|
||||
AM33XX_IOPAD(0x8cc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
|
||||
/* lcd_data12.lcd_data12 */
|
||||
AM33XX_IOPAD(0x8d0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
|
||||
/* lcd_data13.lcd_data13 */
|
||||
AM33XX_IOPAD(0x8d4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
|
||||
/* lcd_data14.lcd_data14 */
|
||||
AM33XX_IOPAD(0x8d8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
|
||||
/* lcd_data15.lcd_data15 */
|
||||
AM33XX_IOPAD(0x8dc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
|
||||
/* lcd_vsync.lcd_vsync */
|
||||
AM33XX_IOPAD(0x8e0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
|
||||
/* lcd_hsync.lcd_hsync */
|
||||
AM33XX_IOPAD(0x8e4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
|
||||
/* lcd_pclk.lcd_pclk */
|
||||
AM33XX_IOPAD(0x8e8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
|
||||
/* lcd_ac_bias_en.lcd_ac_bias_en */
|
||||
AM33XX_IOPAD(0x8ec, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
|
||||
>;
|
||||
};
|
||||
|
||||
lcd_pins_sleep: pinmux_lcd_pins_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* lcd_data0.lcd_data0 */
|
||||
AM33XX_IOPAD(0x8a0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
|
||||
/* lcd_data1.lcd_data1 */
|
||||
AM33XX_IOPAD(0x8a4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
|
||||
/* lcd_data2.lcd_data2 */
|
||||
AM33XX_IOPAD(0x8a8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
|
||||
/* lcd_data3.lcd_data3 */
|
||||
AM33XX_IOPAD(0x8ac, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
|
||||
/* lcd_data4.lcd_data4 */
|
||||
AM33XX_IOPAD(0x8b0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
|
||||
/* lcd_data5.lcd_data5 */
|
||||
AM33XX_IOPAD(0x8b4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
|
||||
/* lcd_data6.lcd_data6 */
|
||||
AM33XX_IOPAD(0x8b8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
|
||||
/* lcd_data7.lcd_data7 */
|
||||
AM33XX_IOPAD(0x8bc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
|
||||
/* lcd_data8.lcd_data8 */
|
||||
AM33XX_IOPAD(0x8c0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
|
||||
/* lcd_data9.lcd_data9 */
|
||||
AM33XX_IOPAD(0x8c4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
|
||||
/* lcd_data10.lcd_data10 */
|
||||
AM33XX_IOPAD(0x8c8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
|
||||
/* lcd_data11.lcd_data11 */
|
||||
AM33XX_IOPAD(0x8cc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
|
||||
/* lcd_data12.lcd_data12 */
|
||||
AM33XX_IOPAD(0x8d0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
|
||||
/* lcd_data13.lcd_data13 */
|
||||
AM33XX_IOPAD(0x8d4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
|
||||
/* lcd_data14.lcd_data14 */
|
||||
AM33XX_IOPAD(0x8d8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
|
||||
/* lcd_data15.lcd_data15 */
|
||||
AM33XX_IOPAD(0x8dc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
|
||||
/* lcd_vsync.lcd_vsync */
|
||||
AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7)
|
||||
/* lcd_hsync.lcd_hsync */
|
||||
AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7)
|
||||
/* lcd_pclk.lcd_pclk */
|
||||
AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7)
|
||||
/* lcd_ac_bias_en.lcd_ac_bias_en */
|
||||
AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
leds_pins: pinmux_leds_pins {
|
||||
guardian_led_pins: pinmux_guardian_led_pins {
|
||||
pinctrl-single,pins = <
|
||||
AM33XX_IOPAD(0x868, PIN_OUTPUT | MUX_MODE7)
|
||||
AM33XX_IOPAD(0x86c, PIN_OUTPUT | MUX_MODE7)
|
||||
AM33XX_IOPAD(0x868, PIN_OUTPUT | MUX_MODE7) /* (T16) gpmc_a10.gpio1[26] */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc1_pins: pinmux_mmc1_pins {
|
||||
pinctrl-single,pins = <
|
||||
AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0)
|
||||
AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0)
|
||||
AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0)
|
||||
AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0)
|
||||
AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)
|
||||
AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)
|
||||
AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7)
|
||||
AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
|
||||
AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
|
||||
AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
|
||||
AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
|
||||
AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
|
||||
AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
|
||||
AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* GPIO0_6 */
|
||||
>;
|
||||
};
|
||||
|
||||
spi0_pins: pinmux_spi0_pins {
|
||||
pinctrl-single,pins = <
|
||||
/* SPI0_CLK - spi0_clk.spi */
|
||||
AM33XX_IOPAD(0x950, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
|
||||
/* SPI0_MOSI - spi0_d0.spi0 */
|
||||
AM33XX_IOPAD(0x954, PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
/* SPI0_MISO - spi0_d1.spi0 */
|
||||
AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0)
|
||||
/* SPI0_CS0 - spi */
|
||||
AM33XX_IOPAD(0x95c, PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
>;
|
||||
};
|
||||
|
||||
uart0_pins: pinmux_uart0_pins {
|
||||
pinctrl-single,pins = <
|
||||
/* uart0_rxd.uart0_rxd */
|
||||
AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)
|
||||
/* uart0_txd.uart0_txd */
|
||||
AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
|
||||
>;
|
||||
};
|
||||
|
||||
uart2_pins: pinmux_uart2_pins {
|
||||
pinctrl-single,pins = <
|
||||
/* K18 uart2_rxd.mirx_txd */
|
||||
AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE1)
|
||||
/* L18 uart2_txd.mirx_rxd */
|
||||
AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLDOWN | MUX_MODE1)
|
||||
>;
|
||||
};
|
||||
|
||||
nandflash_pins: pinmux_nandflash_pins {
|
||||
pinctrl-single,pins = <
|
||||
/* (U7) gpmc_ad0.gpmc_ad0 */
|
||||
AM33XX_IOPAD(0x800, PIN_INPUT | MUX_MODE0)
|
||||
/* (V7) gpmc_ad1.gpmc_ad1 */
|
||||
AM33XX_IOPAD(0x804, PIN_INPUT | MUX_MODE0)
|
||||
/* (R8) gpmc_ad2.gpmc_ad2 */
|
||||
AM33XX_IOPAD(0x808, PIN_INPUT | MUX_MODE0)
|
||||
/* (T8) gpmc_ad3.gpmc_ad3 */
|
||||
AM33XX_IOPAD(0x80c, PIN_INPUT | MUX_MODE0)
|
||||
/* (U8) gpmc_ad4.gpmc_ad4 */
|
||||
AM33XX_IOPAD(0x810, PIN_INPUT | MUX_MODE0)
|
||||
/* (V8) gpmc_ad5.gpmc_ad5 */
|
||||
AM33XX_IOPAD(0x814, PIN_INPUT | MUX_MODE0)
|
||||
/* (R9) gpmc_ad6.gpmc_ad6 */
|
||||
AM33XX_IOPAD(0x818, PIN_INPUT | MUX_MODE0)
|
||||
/* (T9) gpmc_ad7.gpmc_ad7 */
|
||||
AM33XX_IOPAD(0x81c, PIN_INPUT | MUX_MODE0)
|
||||
/* (T17) gpmc_wait0.gpmc_wait0 */
|
||||
AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE0)
|
||||
/* (U17) gpmc_wpn.gpmc_wpn */
|
||||
AM33XX_IOPAD(0x874, PIN_OUTPUT | MUX_MODE0)
|
||||
/* (V6) gpmc_csn0.gpmc_csn0 */
|
||||
AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)
|
||||
/* (R7) gpmc_advn_ale.gpmc_advn_ale */
|
||||
AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)
|
||||
/* (T7) gpmc_oen_ren.gpmc_oen_ren */
|
||||
AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)
|
||||
/* (U6) gpmc_wen.gpmc_wen */
|
||||
AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)
|
||||
/* (T6) gpmc_be0n_cle.gpmc_be0n_cle */
|
||||
AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)
|
||||
>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -182,7 +182,7 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_pins>;
|
||||
|
||||
m25p80@0 {
|
||||
flash@0 {
|
||||
compatible = "mx25l6405d";
|
||||
spi-max-frequency = <40000000>;
|
||||
|
||||
|
|
|
|||
|
|
@ -394,7 +394,7 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_pins>;
|
||||
|
||||
m25p80@0 {
|
||||
flash@0 {
|
||||
compatible = "mx25l6405d";
|
||||
spi-max-frequency = <40000000>;
|
||||
|
||||
|
|
|
|||
|
|
@ -27,6 +27,13 @@
|
|||
reg = <0x80000000 0x10000000>;
|
||||
};
|
||||
|
||||
clk32k: clk32k {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
vdd_mod: vdd_mod_reg {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd-mod";
|
||||
|
|
@ -124,9 +131,6 @@
|
|||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
ti,elm-id = <&elm>;
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -149,6 +153,8 @@
|
|||
};
|
||||
|
||||
&rtc {
|
||||
clocks = <&clk32k>;
|
||||
clock-names = "ext-clk";
|
||||
system-power-controller;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -227,14 +227,20 @@
|
|||
};
|
||||
|
||||
&nand0 {
|
||||
partition@0 {
|
||||
label = "MLO";
|
||||
reg = <0x00000 0x20000>;
|
||||
};
|
||||
nand_parts: partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@20000 {
|
||||
label = "boot";
|
||||
reg = <0x20000 0x80000>;
|
||||
partition@0 {
|
||||
label = "MLO";
|
||||
reg = <0x00000 0x20000>;
|
||||
};
|
||||
|
||||
partition@80000 {
|
||||
label = "boot";
|
||||
reg = <0x80000 0x100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -331,7 +331,7 @@
|
|||
pinctrl-0 = <&spi0_pins>;
|
||||
status = "okay";
|
||||
|
||||
serial_flash: m25p80@0 {
|
||||
serial_flash: flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <48000000>;
|
||||
reg = <0x0>;
|
||||
|
|
|
|||
|
|
@ -588,7 +588,7 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_pins>;
|
||||
|
||||
flash: n25q032@1 {
|
||||
flash: flash@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "micron,n25q032";
|
||||
|
|
|
|||
|
|
@ -5,251 +5,288 @@
|
|||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*/
|
||||
&scm_clocks {
|
||||
sys_clkin_ck: sys_clkin_ck@40 {
|
||||
sys_clkin_ck: clock-sys-clkin-22@40 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clock-output-names = "sys_clkin_ck";
|
||||
clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
|
||||
ti,bit-shift = <22>;
|
||||
reg = <0x0040>;
|
||||
};
|
||||
|
||||
adc_tsc_fck: adc_tsc_fck {
|
||||
adc_tsc_fck: clock-adc-tsc-fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-output-names = "adc_tsc_fck";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dcan0_fck: dcan0_fck {
|
||||
dcan0_fck: clock-dcan0-fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-output-names = "dcan0_fck";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dcan1_fck: dcan1_fck {
|
||||
dcan1_fck: clock-dcan1-fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-output-names = "dcan1_fck";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
mcasp0_fck: mcasp0_fck {
|
||||
mcasp0_fck: clock-mcasp0-fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-output-names = "mcasp0_fck";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
mcasp1_fck: mcasp1_fck {
|
||||
mcasp1_fck: clock-mcasp1-fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-output-names = "mcasp1_fck";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
smartreflex0_fck: smartreflex0_fck {
|
||||
smartreflex0_fck: clock-smartreflex0-fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-output-names = "smartreflex0_fck";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
smartreflex1_fck: smartreflex1_fck {
|
||||
smartreflex1_fck: clock-smartreflex1-fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-output-names = "smartreflex1_fck";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
sha0_fck: sha0_fck {
|
||||
sha0_fck: clock-sha0-fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-output-names = "sha0_fck";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
aes0_fck: aes0_fck {
|
||||
aes0_fck: clock-aes0-fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-output-names = "aes0_fck";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
rng_fck: rng_fck {
|
||||
rng_fck: clock-rng-fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-output-names = "rng_fck";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&l4ls_gclk>;
|
||||
ti,bit-shift = <0>;
|
||||
reg = <0x0664>;
|
||||
};
|
||||
clock@664 {
|
||||
compatible = "ti,clksel";
|
||||
reg = <0x664>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
|
||||
ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&l4ls_gclk>;
|
||||
ti,bit-shift = <1>;
|
||||
reg = <0x0664>;
|
||||
};
|
||||
ehrpwm0_tbclk: clock-ehrpwm0-tbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clock-output-names = "ehrpwm0_tbclk";
|
||||
clocks = <&l4ls_gclk>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&l4ls_gclk>;
|
||||
ti,bit-shift = <2>;
|
||||
reg = <0x0664>;
|
||||
ehrpwm1_tbclk: clock-ehrpwm1-tbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clock-output-names = "ehrpwm1_tbclk";
|
||||
clocks = <&l4ls_gclk>;
|
||||
ti,bit-shift = <1>;
|
||||
};
|
||||
|
||||
ehrpwm2_tbclk: clock-ehrpwm2-tbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clock-output-names = "ehrpwm2_tbclk";
|
||||
clocks = <&l4ls_gclk>;
|
||||
ti,bit-shift = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
&prcm_clocks {
|
||||
clk_32768_ck: clk_32768_ck {
|
||||
clk_32768_ck: clock-clk-32768 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "clk_32768_ck";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
clk_rc32k_ck: clk_rc32k_ck {
|
||||
clk_rc32k_ck: clock-clk-rc32k {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "clk_rc32k_ck";
|
||||
clock-frequency = <32000>;
|
||||
};
|
||||
|
||||
virt_19200000_ck: virt_19200000_ck {
|
||||
virt_19200000_ck: clock-virt-19200000 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "virt_19200000_ck";
|
||||
clock-frequency = <19200000>;
|
||||
};
|
||||
|
||||
virt_24000000_ck: virt_24000000_ck {
|
||||
virt_24000000_ck: clock-virt-24000000 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "virt_24000000_ck";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
virt_25000000_ck: virt_25000000_ck {
|
||||
virt_25000000_ck: clock-virt-25000000 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "virt_25000000_ck";
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
virt_26000000_ck: virt_26000000_ck {
|
||||
virt_26000000_ck: clock-virt-26000000 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "virt_26000000_ck";
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
|
||||
tclkin_ck: tclkin_ck {
|
||||
tclkin_ck: clock-tclkin {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "tclkin_ck";
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
|
||||
dpll_core_ck: dpll_core_ck@490 {
|
||||
dpll_core_ck: clock@490 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-core-clock";
|
||||
clock-output-names = "dpll_core_ck";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>;
|
||||
};
|
||||
|
||||
dpll_core_x2_ck: dpll_core_x2_ck {
|
||||
dpll_core_x2_ck: clock-dpll-core-x2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-x2-clock";
|
||||
clock-output-names = "dpll_core_x2_ck";
|
||||
clocks = <&dpll_core_ck>;
|
||||
};
|
||||
|
||||
dpll_core_m4_ck: dpll_core_m4_ck@480 {
|
||||
dpll_core_m4_ck: clock-dpll-core-m4@480 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clock-output-names = "dpll_core_m4_ck";
|
||||
clocks = <&dpll_core_x2_ck>;
|
||||
ti,max-div = <31>;
|
||||
reg = <0x0480>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
dpll_core_m5_ck: dpll_core_m5_ck@484 {
|
||||
dpll_core_m5_ck: clock-dpll-core-m5@484 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clock-output-names = "dpll_core_m5_ck";
|
||||
clocks = <&dpll_core_x2_ck>;
|
||||
ti,max-div = <31>;
|
||||
reg = <0x0484>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
dpll_core_m6_ck: dpll_core_m6_ck@4d8 {
|
||||
dpll_core_m6_ck: clock-dpll-core-m6@4d8 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clock-output-names = "dpll_core_m6_ck";
|
||||
clocks = <&dpll_core_x2_ck>;
|
||||
ti,max-div = <31>;
|
||||
reg = <0x04d8>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
dpll_mpu_ck: dpll_mpu_ck@488 {
|
||||
dpll_mpu_ck: clock@488 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-clock";
|
||||
clock-output-names = "dpll_mpu_ck";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>;
|
||||
};
|
||||
|
||||
dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 {
|
||||
dpll_mpu_m2_ck: clock-dpll-mpu-m2@4a8 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clock-output-names = "dpll_mpu_m2_ck";
|
||||
clocks = <&dpll_mpu_ck>;
|
||||
ti,max-div = <31>;
|
||||
reg = <0x04a8>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
dpll_ddr_ck: dpll_ddr_ck@494 {
|
||||
dpll_ddr_ck: clock@494 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-no-gate-clock";
|
||||
clock-output-names = "dpll_ddr_ck";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>;
|
||||
};
|
||||
|
||||
dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 {
|
||||
dpll_ddr_m2_ck: clock-dpll-ddr-m2@4a0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clock-output-names = "dpll_ddr_m2_ck";
|
||||
clocks = <&dpll_ddr_ck>;
|
||||
ti,max-div = <31>;
|
||||
reg = <0x04a0>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck {
|
||||
dpll_ddr_m2_div2_ck: clock-dpll-ddr-m2-div2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-output-names = "dpll_ddr_m2_div2_ck";
|
||||
clocks = <&dpll_ddr_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
dpll_disp_ck: dpll_disp_ck@498 {
|
||||
dpll_disp_ck: clock@498 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-no-gate-clock";
|
||||
clock-output-names = "dpll_disp_ck";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;
|
||||
};
|
||||
|
||||
dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 {
|
||||
dpll_disp_m2_ck: clock-dpll-disp-m2@4a4 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clock-output-names = "dpll_disp_m2_ck";
|
||||
clocks = <&dpll_disp_ck>;
|
||||
ti,max-div = <31>;
|
||||
reg = <0x04a4>;
|
||||
|
|
@ -257,418 +294,484 @@
|
|||
ti,set-rate-parent;
|
||||
};
|
||||
|
||||
dpll_per_ck: dpll_per_ck@48c {
|
||||
dpll_per_ck: clock@48c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-no-gate-j-type-clock";
|
||||
clock-output-names = "dpll_per_ck";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>;
|
||||
};
|
||||
|
||||
dpll_per_m2_ck: dpll_per_m2_ck@4ac {
|
||||
dpll_per_m2_ck: clock-dpll-per-m2@4ac {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clock-output-names = "dpll_per_m2_ck";
|
||||
clocks = <&dpll_per_ck>;
|
||||
ti,max-div = <31>;
|
||||
reg = <0x04ac>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
|
||||
dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-output-names = "dpll_per_m2_div4_wkupdm_ck";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <4>;
|
||||
};
|
||||
|
||||
dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
|
||||
dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-output-names = "dpll_per_m2_div4_ck";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <4>;
|
||||
};
|
||||
|
||||
clk_24mhz: clk_24mhz {
|
||||
clk_24mhz: clock-clk-24mhz {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-output-names = "clk_24mhz";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <8>;
|
||||
};
|
||||
|
||||
clkdiv32k_ck: clkdiv32k_ck {
|
||||
clkdiv32k_ck: clock-clkdiv32k {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-output-names = "clkdiv32k_ck";
|
||||
clocks = <&clk_24mhz>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <732>;
|
||||
};
|
||||
|
||||
l3_gclk: l3_gclk {
|
||||
l3_gclk: clock-l3-gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-output-names = "l3_gclk";
|
||||
clocks = <&dpll_core_m4_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
pruss_ocp_gclk: pruss_ocp_gclk@530 {
|
||||
pruss_ocp_gclk: clock-pruss-ocp-gclk@530 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clock-output-names = "pruss_ocp_gclk";
|
||||
clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
|
||||
reg = <0x0530>;
|
||||
};
|
||||
|
||||
mmu_fck: mmu_fck@914 {
|
||||
mmu_fck: clock-mmu-fck-1@914 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clock-output-names = "mmu_fck";
|
||||
clocks = <&dpll_core_m4_ck>;
|
||||
ti,bit-shift = <1>;
|
||||
reg = <0x0914>;
|
||||
};
|
||||
|
||||
timer1_fck: timer1_fck@528 {
|
||||
timer1_fck: clock-timer1-fck@528 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clock-output-names = "timer1_fck";
|
||||
clocks = <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
|
||||
reg = <0x0528>;
|
||||
};
|
||||
|
||||
timer2_fck: timer2_fck@508 {
|
||||
timer2_fck: clock-timer2-fck@508 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clock-output-names = "timer2_fck";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
|
||||
reg = <0x0508>;
|
||||
};
|
||||
|
||||
timer3_fck: timer3_fck@50c {
|
||||
timer3_fck: clock-timer3-fck@50c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clock-output-names = "timer3_fck";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
|
||||
reg = <0x050c>;
|
||||
};
|
||||
|
||||
timer4_fck: timer4_fck@510 {
|
||||
timer4_fck: clock-timer4-fck@510 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clock-output-names = "timer4_fck";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
|
||||
reg = <0x0510>;
|
||||
};
|
||||
|
||||
timer5_fck: timer5_fck@518 {
|
||||
timer5_fck: clock-timer5-fck@518 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clock-output-names = "timer5_fck";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
|
||||
reg = <0x0518>;
|
||||
};
|
||||
|
||||
timer6_fck: timer6_fck@51c {
|
||||
timer6_fck: clock-timer6-fck@51c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clock-output-names = "timer6_fck";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
|
||||
reg = <0x051c>;
|
||||
};
|
||||
|
||||
timer7_fck: timer7_fck@504 {
|
||||
timer7_fck: clock-timer7-fck@504 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clock-output-names = "timer7_fck";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
|
||||
reg = <0x0504>;
|
||||
};
|
||||
|
||||
usbotg_fck: usbotg_fck@47c {
|
||||
usbotg_fck: clock-usbotg-fck-8@47c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clock-output-names = "usbotg_fck";
|
||||
clocks = <&dpll_per_ck>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x047c>;
|
||||
};
|
||||
|
||||
dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
|
||||
dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-output-names = "dpll_core_m4_div2_ck";
|
||||
clocks = <&dpll_core_m4_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
ieee5000_fck: ieee5000_fck@e4 {
|
||||
ieee5000_fck: clock-ieee5000-fck-1@e4 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clock-output-names = "ieee5000_fck";
|
||||
clocks = <&dpll_core_m4_div2_ck>;
|
||||
ti,bit-shift = <1>;
|
||||
reg = <0x00e4>;
|
||||
};
|
||||
|
||||
wdt1_fck: wdt1_fck@538 {
|
||||
wdt1_fck: clock-wdt1-fck@538 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clock-output-names = "wdt1_fck";
|
||||
clocks = <&clk_rc32k_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
|
||||
reg = <0x0538>;
|
||||
};
|
||||
|
||||
l4_rtc_gclk: l4_rtc_gclk {
|
||||
l4_rtc_gclk: clock-l4-rtc-gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-output-names = "l4_rtc_gclk";
|
||||
clocks = <&dpll_core_m4_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
l4hs_gclk: l4hs_gclk {
|
||||
l4hs_gclk: clock-l4hs-gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-output-names = "l4hs_gclk";
|
||||
clocks = <&dpll_core_m4_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
l3s_gclk: l3s_gclk {
|
||||
l3s_gclk: clock-l3s-gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-output-names = "l3s_gclk";
|
||||
clocks = <&dpll_core_m4_div2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
l4fw_gclk: l4fw_gclk {
|
||||
l4fw_gclk: clock-l4fw-gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-output-names = "l4fw_gclk";
|
||||
clocks = <&dpll_core_m4_div2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
l4ls_gclk: l4ls_gclk {
|
||||
l4ls_gclk: clock-l4ls-gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-output-names = "l4ls_gclk";
|
||||
clocks = <&dpll_core_m4_div2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
sysclk_div_ck: sysclk_div_ck {
|
||||
sysclk_div_ck: clock-sysclk-div {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-output-names = "sysclk_div_ck";
|
||||
clocks = <&dpll_core_m4_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
cpsw_125mhz_gclk: cpsw_125mhz_gclk {
|
||||
cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-output-names = "cpsw_125mhz_gclk";
|
||||
clocks = <&dpll_core_m5_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@520 {
|
||||
cpsw_cpts_rft_clk: clock-cpsw-cpts-rft@520 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clock-output-names = "cpsw_cpts_rft_clk";
|
||||
clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
|
||||
reg = <0x0520>;
|
||||
};
|
||||
|
||||
gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c {
|
||||
gpio0_dbclk_mux_ck: clock-gpio0-dbclk-mux@53c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clock-output-names = "gpio0_dbclk_mux_ck";
|
||||
clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
|
||||
reg = <0x053c>;
|
||||
};
|
||||
|
||||
lcd_gclk: lcd_gclk@534 {
|
||||
lcd_gclk: clock-lcd-gclk@534 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clock-output-names = "lcd_gclk";
|
||||
clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
|
||||
reg = <0x0534>;
|
||||
ti,set-rate-parent;
|
||||
};
|
||||
|
||||
mmc_clk: mmc_clk {
|
||||
mmc_clk: clock-mmc {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-output-names = "mmc_clk";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@52c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
|
||||
ti,bit-shift = <1>;
|
||||
reg = <0x052c>;
|
||||
clock@52c {
|
||||
compatible = "ti,clksel";
|
||||
reg = <0x52c>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
|
||||
gfx_fclk_clksel_ck: clock-gfx-fclk-clksel {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clock-output-names = "gfx_fclk_clksel_ck";
|
||||
clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
|
||||
ti,bit-shift = <1>;
|
||||
};
|
||||
|
||||
gfx_fck_div_ck: clock-gfx-fck-div {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clock-output-names = "gfx_fck_div_ck";
|
||||
clocks = <&gfx_fclk_clksel_ck>;
|
||||
ti,max-div = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
gfx_fck_div_ck: gfx_fck_div_ck@52c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&gfx_fclk_clksel_ck>;
|
||||
reg = <0x052c>;
|
||||
ti,max-div = <2>;
|
||||
};
|
||||
clock@700 {
|
||||
compatible = "ti,clksel";
|
||||
reg = <0x700>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
|
||||
sysclkout_pre_ck: sysclkout_pre_ck@700 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
|
||||
reg = <0x0700>;
|
||||
};
|
||||
sysclkout_pre_ck: clock-sysclkout-pre {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clock-output-names = "sysclkout_pre_ck";
|
||||
clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
|
||||
};
|
||||
|
||||
clkout2_div_ck: clkout2_div_ck@700 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&sysclkout_pre_ck>;
|
||||
ti,bit-shift = <3>;
|
||||
ti,max-div = <8>;
|
||||
reg = <0x0700>;
|
||||
};
|
||||
clkout2_div_ck: clock-clkout2-div {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clock-output-names = "clkout2_div_ck";
|
||||
clocks = <&sysclkout_pre_ck>;
|
||||
ti,bit-shift = <3>;
|
||||
ti,max-div = <8>;
|
||||
};
|
||||
|
||||
clkout2_ck: clkout2_ck@700 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&clkout2_div_ck>;
|
||||
ti,bit-shift = <7>;
|
||||
reg = <0x0700>;
|
||||
clkout2_ck: clock-clkout2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clock-output-names = "clkout2_ck";
|
||||
clocks = <&clkout2_div_ck>;
|
||||
ti,bit-shift = <7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&prcm {
|
||||
per_cm: per-cm@0 {
|
||||
per_cm: clock@0 {
|
||||
compatible = "ti,omap4-cm";
|
||||
clock-output-names = "per_cm";
|
||||
reg = <0x0 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x0 0x400>;
|
||||
|
||||
l4ls_clkctrl: l4ls-clkctrl@38 {
|
||||
l4ls_clkctrl: clock@38 {
|
||||
compatible = "ti,clkctrl";
|
||||
clock-output-names = "l4ls_clkctrl";
|
||||
reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
|
||||
l3s_clkctrl: l3s-clkctrl@1c {
|
||||
l3s_clkctrl: clock@1c {
|
||||
compatible = "ti,clkctrl";
|
||||
clock-output-names = "l3s_clkctrl";
|
||||
reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
|
||||
l3_clkctrl: l3-clkctrl@24 {
|
||||
l3_clkctrl: clock@24 {
|
||||
compatible = "ti,clkctrl";
|
||||
clock-output-names = "l3_clkctrl";
|
||||
reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
|
||||
l4hs_clkctrl: l4hs-clkctrl@120 {
|
||||
l4hs_clkctrl: clock@120 {
|
||||
compatible = "ti,clkctrl";
|
||||
clock-output-names = "l4hs_clkctrl";
|
||||
reg = <0x120 0x4>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
|
||||
pruss_ocp_clkctrl: pruss-ocp-clkctrl@e8 {
|
||||
pruss_ocp_clkctrl: clock@e8 {
|
||||
compatible = "ti,clkctrl";
|
||||
clock-output-names = "pruss_ocp_clkctrl";
|
||||
reg = <0xe8 0x4>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
|
||||
cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@0 {
|
||||
cpsw_125mhz_clkctrl: clock@0 {
|
||||
compatible = "ti,clkctrl";
|
||||
clock-output-names = "cpsw_125mhz_clkctrl";
|
||||
reg = <0x0 0x18>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
|
||||
lcdc_clkctrl: lcdc-clkctrl@18 {
|
||||
lcdc_clkctrl: clock@18 {
|
||||
compatible = "ti,clkctrl";
|
||||
clock-output-names = "lcdc_clkctrl";
|
||||
reg = <0x18 0x4>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
|
||||
clk_24mhz_clkctrl: clk-24mhz-clkctrl@14c {
|
||||
clk_24mhz_clkctrl: clock@14c {
|
||||
compatible = "ti,clkctrl";
|
||||
clock-output-names = "clk_24mhz_clkctrl";
|
||||
reg = <0x14c 0x4>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
wkup_cm: wkup-cm@400 {
|
||||
wkup_cm: clock@400 {
|
||||
compatible = "ti,omap4-cm";
|
||||
clock-output-names = "wkup_cm";
|
||||
reg = <0x400 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x400 0x100>;
|
||||
|
||||
l4_wkup_clkctrl: l4-wkup-clkctrl@0 {
|
||||
l4_wkup_clkctrl: clock@0 {
|
||||
compatible = "ti,clkctrl";
|
||||
clock-output-names = "l4_wkup_clkctrl";
|
||||
reg = <0x0 0x10>, <0xb4 0x24>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
|
||||
l3_aon_clkctrl: l3-aon-clkctrl@14 {
|
||||
l3_aon_clkctrl: clock@14 {
|
||||
compatible = "ti,clkctrl";
|
||||
clock-output-names = "l3_aon_clkctrl";
|
||||
reg = <0x14 0x4>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
|
||||
l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@b0 {
|
||||
l4_wkup_aon_clkctrl: clock@b0 {
|
||||
compatible = "ti,clkctrl";
|
||||
clock-output-names = "l4_wkup_aon_clkctrl";
|
||||
reg = <0xb0 0x4>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
mpu_cm: mpu-cm@600 {
|
||||
mpu_cm: clock@600 {
|
||||
compatible = "ti,omap4-cm";
|
||||
clock-output-names = "mpu_cm";
|
||||
reg = <0x600 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x600 0x100>;
|
||||
|
||||
mpu_clkctrl: mpu-clkctrl@0 {
|
||||
mpu_clkctrl: clock@0 {
|
||||
compatible = "ti,clkctrl";
|
||||
clock-output-names = "mpu_clkctrl";
|
||||
reg = <0x0 0x8>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
l4_rtc_cm: l4-rtc-cm@800 {
|
||||
l4_rtc_cm: clock@800 {
|
||||
compatible = "ti,omap4-cm";
|
||||
clock-output-names = "l4_rtc_cm";
|
||||
reg = <0x800 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x800 0x100>;
|
||||
|
||||
l4_rtc_clkctrl: l4-rtc-clkctrl@0 {
|
||||
l4_rtc_clkctrl: clock@0 {
|
||||
compatible = "ti,clkctrl";
|
||||
clock-output-names = "l4_rtc_clkctrl";
|
||||
reg = <0x0 0x4>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
gfx_l3_cm: gfx-l3-cm@900 {
|
||||
gfx_l3_cm: clock@900 {
|
||||
compatible = "ti,omap4-cm";
|
||||
clock-output-names = "gfx_l3_cm";
|
||||
reg = <0x900 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x900 0x100>;
|
||||
|
||||
gfx_l3_clkctrl: gfx-l3-clkctrl@0 {
|
||||
gfx_l3_clkctrl: clock@0 {
|
||||
compatible = "ti,clkctrl";
|
||||
clock-output-names = "gfx_l3_clkctrl";
|
||||
reg = <0x0 0x8>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
l4_cefuse_cm: l4-cefuse-cm@a00 {
|
||||
l4_cefuse_cm: clock@a00 {
|
||||
compatible = "ti,omap4-cm";
|
||||
clock-output-names = "l4_cefuse_cm";
|
||||
reg = <0xa00 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0xa00 0x100>;
|
||||
|
||||
l4_cefuse_clkctrl: l4-cefuse-clkctrl@0 {
|
||||
l4_cefuse_clkctrl: clock@0 {
|
||||
compatible = "ti,clkctrl";
|
||||
clock-output-names = "l4_cefuse_clkctrl";
|
||||
reg = <0x0 0x24>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -461,8 +461,11 @@
|
|||
interrupts = <17>;
|
||||
interrupt-names = "glue";
|
||||
#dma-cells = <2>;
|
||||
/* For backwards compatibility: */
|
||||
#dma-channels = <30>;
|
||||
dma-channels = <30>;
|
||||
#dma-requests = <256>;
|
||||
dma-requests = <256>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -62,12 +62,27 @@
|
|||
};
|
||||
};
|
||||
&cm_clocks {
|
||||
ipss_ick: ipss_ick@a10 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am35xx-interface-clock";
|
||||
clocks = <&core_l3_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <4>;
|
||||
clock@a10 {
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xa10>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
|
||||
ipss_ick: clock-ipss-ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am35xx-interface-clock";
|
||||
clock-output-names = "ipss_ick";
|
||||
clocks = <&core_l3_ick>;
|
||||
ti,bit-shift = <4>;
|
||||
};
|
||||
|
||||
uart4_ick_am35xx: clock-uart4-ick-am35xx {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clock-output-names = "uart4_ick_am35xx";
|
||||
clocks = <&core_l4_ick>;
|
||||
ti,bit-shift = <23>;
|
||||
};
|
||||
};
|
||||
|
||||
rmii_ck: rmii_ck {
|
||||
|
|
@ -82,20 +97,19 @@
|
|||
clock-frequency = <27000000>;
|
||||
};
|
||||
|
||||
uart4_ick_am35xx: uart4_ick_am35xx@a10 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&core_l4_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <23>;
|
||||
};
|
||||
clock@a00 {
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xa00>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
|
||||
uart4_fck_am35xx: uart4_fck_am35xx@a00 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&core_48m_fck>;
|
||||
reg = <0x0a00>;
|
||||
ti,bit-shift = <23>;
|
||||
uart4_fck_am35xx: clock-uart4-fck-am35xx {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clock-output-names = "uart4_fck_am35xx";
|
||||
clocks = <&core_48m_fck>;
|
||||
ti,bit-shift = <23>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -434,7 +434,7 @@
|
|||
};
|
||||
|
||||
&mcspi1 {
|
||||
s25fl256@0 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
|
|
|
|||
|
|
@ -302,7 +302,7 @@
|
|||
&edma 17 0>;
|
||||
dma-names = "tx0", "rx0";
|
||||
|
||||
flash: w25q64cvzpig@0 {
|
||||
flash: flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
|
|
|
|||
|
|
@ -1127,6 +1127,11 @@
|
|||
cpu0-supply = <&dcdc2>;
|
||||
};
|
||||
|
||||
&wkup_m3_ipc {
|
||||
ti,set-io-isolation;
|
||||
firmware-name = "am43x-evm-scale-data.bin";
|
||||
};
|
||||
|
||||
&pruss1_mdio {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -437,7 +437,7 @@
|
|||
pinctrl-1 = <&qspi_pins_sleep>;
|
||||
|
||||
spi-max-frequency = <48000000>;
|
||||
m25p80@0 {
|
||||
flash@0 {
|
||||
compatible = "mx66l51235l";
|
||||
spi-max-frequency = <48000000>;
|
||||
reg = <0>;
|
||||
|
|
|
|||
|
|
@ -746,7 +746,7 @@
|
|||
pinctrl-0 = <&qspi_pins>;
|
||||
|
||||
spi-max-frequency = <48000000>;
|
||||
m25p80@0 {
|
||||
flash@0 {
|
||||
compatible = "mx66l51235l";
|
||||
spi-max-frequency = <48000000>;
|
||||
reg = <0>;
|
||||
|
|
@ -893,6 +893,10 @@
|
|||
};
|
||||
};
|
||||
|
||||
&wkup_m3_ipc {
|
||||
firmware-name = "am43x-evm-scale-data.bin";
|
||||
};
|
||||
|
||||
&pruss1_mdio {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -902,7 +902,7 @@
|
|||
pinctrl-1 = <&qspi1_pins_sleep>;
|
||||
|
||||
spi-max-frequency = <48000000>;
|
||||
m25p80@0 {
|
||||
flash@0 {
|
||||
compatible = "mx66l51235l";
|
||||
spi-max-frequency = <48000000>;
|
||||
reg = <0>;
|
||||
|
|
@ -1019,6 +1019,10 @@
|
|||
cpu0-supply = <&dcdc2>;
|
||||
};
|
||||
|
||||
&wkup_m3_ipc {
|
||||
firmware-name = "am43x-evm-scale-data.bin";
|
||||
};
|
||||
|
||||
&pruss1_mdio {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -18,7 +18,7 @@
|
|||
|
||||
&qspi {
|
||||
spi-max-frequency = <96000000>;
|
||||
m25p80@0 {
|
||||
flash@0 {
|
||||
spi-max-frequency = <96000000>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -491,7 +491,7 @@
|
|||
|
||||
spi-max-frequency = <48000000>;
|
||||
|
||||
spi_flash: spi_flash@0 {
|
||||
spi_flash: flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,m25p80", "jedec,spi-nor";
|
||||
|
|
|
|||
|
|
@ -526,7 +526,7 @@
|
|||
status = "okay";
|
||||
|
||||
spi-max-frequency = <76800000>;
|
||||
m25p80@0 {
|
||||
flash@0 {
|
||||
compatible = "s25fl256s1", "jedec,spi-nor";
|
||||
spi-max-frequency = <76800000>;
|
||||
reg = <0>;
|
||||
|
|
|
|||
|
|
@ -203,7 +203,7 @@
|
|||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "mx25l25635e", "jedec,spi-nor";
|
||||
|
|
|
|||
|
|
@ -159,7 +159,7 @@
|
|||
pinctrl-0 = <&spi0_pins2>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
spi-flash@0 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
/* MX25L8006E */
|
||||
|
|
|
|||
|
|
@ -258,7 +258,7 @@
|
|||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "micron,n25q064", "jedec,spi-nor";
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@
|
|||
|
||||
status = "disabled";
|
||||
|
||||
spi-flash@0 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "n25q128a13", "jedec,spi-nor";
|
||||
|
|
|
|||
|
|
@ -242,7 +242,7 @@
|
|||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
|
|
|
|||
|
|
@ -168,7 +168,7 @@
|
|||
pinctrl-0 = <&spi1_pins>;
|
||||
status = "okay";
|
||||
|
||||
spi-flash@1 {
|
||||
flash@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
|
|
|
|||
|
|
@ -365,7 +365,7 @@
|
|||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "w25q32", "jedec,spi-nor";
|
||||
|
|
|
|||
|
|
@ -126,7 +126,7 @@
|
|||
pinctrl-0 = <&spi1_pins>;
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
|
|
|
|||
|
|
@ -192,7 +192,7 @@
|
|||
pinctrl-0 = <&spi1_pins>;
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,m25p128", "jedec,spi-nor";
|
||||
|
|
|
|||
|
|
@ -223,7 +223,7 @@
|
|||
pinctrl-0 = <&spi0_pins>;
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "macronix,mx25l6405d", "jedec,spi-nor";
|
||||
|
|
|
|||
|
|
@ -348,7 +348,11 @@
|
|||
#size-cells = <0>;
|
||||
reg = <5>;
|
||||
|
||||
/* ATSHA204A at address 0x64 */
|
||||
/* ATSHA204A-MAHDA-T crypto module */
|
||||
crypto@64 {
|
||||
compatible = "atmel,atsha204a";
|
||||
reg = <0x64>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@6 {
|
||||
|
|
@ -485,7 +489,7 @@
|
|||
pinctrl-0 = <&spi0_pins &spi0cs0_pins>;
|
||||
status = "okay";
|
||||
|
||||
spi-nor@0 {
|
||||
flash@0 {
|
||||
compatible = "spansion,s25fl164k", "jedec,spi-nor";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -133,7 +133,7 @@
|
|||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "w25q32", "jedec,spi-nor";
|
||||
|
|
|
|||
|
|
@ -395,7 +395,7 @@
|
|||
pinctrl-0 = <&spi0_pins>;
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,m25p128", "jedec,spi-nor";
|
||||
|
|
|
|||
|
|
@ -97,7 +97,7 @@
|
|||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,m25p128", "jedec,spi-nor";
|
||||
|
|
|
|||
|
|
@ -101,7 +101,7 @@
|
|||
/* The microsom has an optional W25Q32 on board, connected to CS0 */
|
||||
pinctrl-0 = <&spi1_pins>;
|
||||
|
||||
w25q32: spi-flash@0 {
|
||||
w25q32: flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "w25q32", "jedec,spi-nor";
|
||||
|
|
|
|||
|
|
@ -81,7 +81,7 @@
|
|||
pinctrl-0 = <&spi1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
spi-flash@1 {
|
||||
flash@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "n25q128a13",
|
||||
|
|
|
|||
|
|
@ -79,7 +79,7 @@
|
|||
pinctrl-0 = <&spi1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
spi-flash@0 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "n25q128a13", "jedec,spi-nor";
|
||||
|
|
|
|||
|
|
@ -134,7 +134,7 @@
|
|||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "n25q128a13", "jedec,spi-nor";
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@
|
|||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
|
|
|
|||
|
|
@ -80,7 +80,7 @@
|
|||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@
|
|||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
|
|
|
|||
|
|
@ -80,7 +80,7 @@
|
|||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@
|
|||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
|
|
|
|||
|
|
@ -80,7 +80,7 @@
|
|||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
|
|
|
|||
|
|
@ -93,7 +93,7 @@
|
|||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "m25p64";
|
||||
|
|
|
|||
|
|
@ -89,7 +89,7 @@
|
|||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "m25p64";
|
||||
|
|
|
|||
|
|
@ -235,7 +235,7 @@
|
|||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "m25p64", "jedec,spi-nor";
|
||||
|
|
|
|||
|
|
@ -220,7 +220,7 @@
|
|||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "n25q128a13", "jedec,spi-nor";
|
||||
|
|
|
|||
|
|
@ -255,7 +255,7 @@
|
|||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "everspin,mr25h256";
|
||||
|
|
|
|||
|
|
@ -274,7 +274,7 @@
|
|||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "micron,n25q064", "jedec,spi-nor";
|
||||
|
|
|
|||
|
|
@ -397,8 +397,8 @@
|
|||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-0 = <&spi_0>;
|
||||
clocks = <&axi81_clk>;
|
||||
clock-names = "apb_pclk";
|
||||
clocks = <&axi81_clk>, <&axi81_clk>;
|
||||
clock-names = "sspclk", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -409,8 +409,8 @@
|
|||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-0 = <&spi_1>;
|
||||
clocks = <&axi81_clk>;
|
||||
clock-names = "apb_pclk";
|
||||
clocks = <&axi81_clk>, <&axi81_clk>;
|
||||
clock-names = "sspclk", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -421,8 +421,8 @@
|
|||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-0 = <&spi_2>;
|
||||
clocks = <&axi81_clk>;
|
||||
clock-names = "apb_pclk";
|
||||
clocks = <&axi81_clk>, <&axi81_clk>;
|
||||
clock-names = "sspclk", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -32,7 +32,6 @@
|
|||
* This is based on the unreleased schematic for the Model A+.
|
||||
*
|
||||
* Legend:
|
||||
* "NC" = not connected (no rail from the SoC)
|
||||
* "FOO" = GPIO line named "FOO" on the schematic
|
||||
* "FOO_N" = GPIO line named "FOO" on schematic, active low
|
||||
*/
|
||||
|
|
@ -67,21 +66,21 @@
|
|||
"GPIO27",
|
||||
"SDA0",
|
||||
"SCL0",
|
||||
"NC", /* GPIO30 */
|
||||
"NC", /* GPIO31 */
|
||||
"", /* GPIO30 */
|
||||
"", /* GPIO31 */
|
||||
"CAM_GPIO1", /* GPIO32 */
|
||||
"NC", /* GPIO33 */
|
||||
"NC", /* GPIO34 */
|
||||
"", /* GPIO33 */
|
||||
"", /* GPIO34 */
|
||||
"PWR_LOW_N", /* GPIO35 */
|
||||
"NC", /* GPIO36 */
|
||||
"NC", /* GPIO37 */
|
||||
"", /* GPIO36 */
|
||||
"", /* GPIO37 */
|
||||
"USB_LIMIT", /* GPIO38 */
|
||||
"NC", /* GPIO39 */
|
||||
"", /* GPIO39 */
|
||||
"PWM0_OUT", /* GPIO40 */
|
||||
"CAM_GPIO0", /* GPIO41 */
|
||||
"NC", /* GPIO42 */
|
||||
"NC", /* GPIO43 */
|
||||
"NC", /* GPIO44 */
|
||||
"", /* GPIO42 */
|
||||
"", /* GPIO43 */
|
||||
"", /* GPIO44 */
|
||||
"PWM1_OUT", /* GPIO45 */
|
||||
"HDMI_HPD_N",
|
||||
"STATUS_LED",
|
||||
|
|
|
|||
|
|
@ -26,7 +26,6 @@
|
|||
* RPI00021 sheet 02
|
||||
*
|
||||
* Legend:
|
||||
* "NC" = not connected (no rail from the SoC)
|
||||
* "FOO" = GPIO line named "FOO" on the schematic
|
||||
* "FOO_N" = GPIO line named "FOO" on schematic, active low
|
||||
*/
|
||||
|
|
@ -42,41 +41,41 @@
|
|||
"SPI_MISO",
|
||||
"SPI_MOSI",
|
||||
"SPI_SCLK",
|
||||
"NC", /* GPIO12 */
|
||||
"NC", /* GPIO13 */
|
||||
"", /* GPIO12 */
|
||||
"", /* GPIO13 */
|
||||
/* Serial port */
|
||||
"TXD0",
|
||||
"RXD0",
|
||||
"STATUS_LED_N",
|
||||
"GPIO17",
|
||||
"GPIO18",
|
||||
"NC", /* GPIO19 */
|
||||
"NC", /* GPIO20 */
|
||||
"", /* GPIO19 */
|
||||
"", /* GPIO20 */
|
||||
"GPIO21",
|
||||
"GPIO22",
|
||||
"GPIO23",
|
||||
"GPIO24",
|
||||
"GPIO25",
|
||||
"NC", /* GPIO26 */
|
||||
"", /* GPIO26 */
|
||||
"CAM_GPIO0",
|
||||
/* Binary number representing build/revision */
|
||||
"CONFIG0",
|
||||
"CONFIG1",
|
||||
"CONFIG2",
|
||||
"CONFIG3",
|
||||
"NC", /* GPIO32 */
|
||||
"NC", /* GPIO33 */
|
||||
"NC", /* GPIO34 */
|
||||
"NC", /* GPIO35 */
|
||||
"NC", /* GPIO36 */
|
||||
"NC", /* GPIO37 */
|
||||
"NC", /* GPIO38 */
|
||||
"NC", /* GPIO39 */
|
||||
"", /* GPIO32 */
|
||||
"", /* GPIO33 */
|
||||
"", /* GPIO34 */
|
||||
"", /* GPIO35 */
|
||||
"", /* GPIO36 */
|
||||
"", /* GPIO37 */
|
||||
"", /* GPIO38 */
|
||||
"", /* GPIO39 */
|
||||
"PWM0_OUT",
|
||||
"NC", /* GPIO41 */
|
||||
"NC", /* GPIO42 */
|
||||
"NC", /* GPIO43 */
|
||||
"NC", /* GPIO44 */
|
||||
"", /* GPIO41 */
|
||||
"", /* GPIO42 */
|
||||
"", /* GPIO43 */
|
||||
"", /* GPIO44 */
|
||||
"PWM1_OUT",
|
||||
"HDMI_HPD_P",
|
||||
"SD_CARD_DET",
|
||||
|
|
|
|||
|
|
@ -34,7 +34,6 @@
|
|||
* RPI-BPLUS sheet 1
|
||||
*
|
||||
* Legend:
|
||||
* "NC" = not connected (no rail from the SoC)
|
||||
* "FOO" = GPIO line named "FOO" on the schematic
|
||||
* "FOO_N" = GPIO line named "FOO" on schematic, active low
|
||||
*/
|
||||
|
|
@ -69,21 +68,21 @@
|
|||
"GPIO27",
|
||||
"SDA0",
|
||||
"SCL0",
|
||||
"NC", /* GPIO30 */
|
||||
"", /* GPIO30 */
|
||||
"LAN_RUN", /* GPIO31 */
|
||||
"CAM_GPIO1", /* GPIO32 */
|
||||
"NC", /* GPIO33 */
|
||||
"NC", /* GPIO34 */
|
||||
"", /* GPIO33 */
|
||||
"", /* GPIO34 */
|
||||
"PWR_LOW_N", /* GPIO35 */
|
||||
"NC", /* GPIO36 */
|
||||
"NC", /* GPIO37 */
|
||||
"", /* GPIO36 */
|
||||
"", /* GPIO37 */
|
||||
"USB_LIMIT", /* GPIO38 */
|
||||
"NC", /* GPIO39 */
|
||||
"", /* GPIO39 */
|
||||
"PWM0_OUT", /* GPIO40 */
|
||||
"CAM_GPIO0", /* GPIO41 */
|
||||
"NC", /* GPIO42 */
|
||||
"NC", /* GPIO43 */
|
||||
"ETHCLK", /* GPIO44 */
|
||||
"", /* GPIO42 */
|
||||
"", /* GPIO43 */
|
||||
"ETH_CLK", /* GPIO44 */
|
||||
"PWM1_OUT", /* GPIO45 */
|
||||
"HDMI_HPD_N",
|
||||
"STATUS_LED",
|
||||
|
|
|
|||
|
|
@ -27,7 +27,6 @@
|
|||
* RPI00022 sheet 02
|
||||
*
|
||||
* Legend:
|
||||
* "NC" = not connected (no rail from the SoC)
|
||||
* "FOO" = GPIO line named "FOO" on the schematic
|
||||
* "FOO_N" = GPIO line named "FOO" on schematic, active low
|
||||
*/
|
||||
|
|
@ -43,40 +42,40 @@
|
|||
"SPI_MISO",
|
||||
"SPI_MOSI",
|
||||
"SPI_SCLK",
|
||||
"NC", /* GPIO12 */
|
||||
"NC", /* GPIO13 */
|
||||
"", /* GPIO12 */
|
||||
"", /* GPIO13 */
|
||||
/* Serial port */
|
||||
"TXD0",
|
||||
"RXD0",
|
||||
"STATUS_LED_N",
|
||||
"GPIO17",
|
||||
"GPIO18",
|
||||
"NC", /* GPIO19 */
|
||||
"NC", /* GPIO20 */
|
||||
"", /* GPIO19 */
|
||||
"", /* GPIO20 */
|
||||
"CAM_GPIO",
|
||||
"GPIO22",
|
||||
"GPIO23",
|
||||
"GPIO24",
|
||||
"GPIO25",
|
||||
"NC", /* GPIO26 */
|
||||
"", /* GPIO26 */
|
||||
"GPIO27",
|
||||
"GPIO28",
|
||||
"GPIO29",
|
||||
"GPIO30",
|
||||
"GPIO31",
|
||||
"NC", /* GPIO32 */
|
||||
"NC", /* GPIO33 */
|
||||
"NC", /* GPIO34 */
|
||||
"NC", /* GPIO35 */
|
||||
"NC", /* GPIO36 */
|
||||
"NC", /* GPIO37 */
|
||||
"NC", /* GPIO38 */
|
||||
"NC", /* GPIO39 */
|
||||
"", /* GPIO32 */
|
||||
"", /* GPIO33 */
|
||||
"", /* GPIO34 */
|
||||
"", /* GPIO35 */
|
||||
"", /* GPIO36 */
|
||||
"", /* GPIO37 */
|
||||
"", /* GPIO38 */
|
||||
"", /* GPIO39 */
|
||||
"PWM0_OUT",
|
||||
"NC", /* GPIO41 */
|
||||
"NC", /* GPIO42 */
|
||||
"NC", /* GPIO43 */
|
||||
"NC", /* GPIO44 */
|
||||
"", /* GPIO41 */
|
||||
"", /* GPIO42 */
|
||||
"", /* GPIO43 */
|
||||
"", /* GPIO44 */
|
||||
"PWM1_OUT",
|
||||
"HDMI_HPD_P",
|
||||
"SD_CARD_DET",
|
||||
|
|
|
|||
|
|
@ -27,7 +27,6 @@
|
|||
* RPI00021 sheet 02
|
||||
*
|
||||
* Legend:
|
||||
* "NC" = not connected (no rail from the SoC)
|
||||
* "FOO" = GPIO line named "FOO" on the schematic
|
||||
* "FOO_N" = GPIO line named "FOO" on schematic, active low
|
||||
*/
|
||||
|
|
@ -43,41 +42,40 @@
|
|||
"SPI_MISO",
|
||||
"SPI_MOSI",
|
||||
"SPI_SCLK",
|
||||
"NC", /* GPIO12 */
|
||||
"NC", /* GPIO13 */
|
||||
"", /* GPIO12 */
|
||||
"", /* GPIO13 */
|
||||
/* Serial port */
|
||||
"TXD0",
|
||||
"RXD0",
|
||||
"STATUS_LED_N",
|
||||
"GPIO17",
|
||||
"GPIO18",
|
||||
"NC", /* GPIO19 */
|
||||
"NC", /* GPIO20 */
|
||||
"GPIO21",
|
||||
"", /* GPIO19 */
|
||||
"", /* GPIO20 */
|
||||
"CAM_GPIO0",
|
||||
"GPIO22",
|
||||
"GPIO23",
|
||||
"GPIO24",
|
||||
"GPIO25",
|
||||
"NC", /* GPIO26 */
|
||||
"CAM_GPIO0",
|
||||
/* Binary number representing build/revision */
|
||||
"CONFIG0",
|
||||
"CONFIG1",
|
||||
"CONFIG2",
|
||||
"CONFIG3",
|
||||
"NC", /* GPIO32 */
|
||||
"NC", /* GPIO33 */
|
||||
"NC", /* GPIO34 */
|
||||
"NC", /* GPIO35 */
|
||||
"NC", /* GPIO36 */
|
||||
"NC", /* GPIO37 */
|
||||
"NC", /* GPIO38 */
|
||||
"NC", /* GPIO39 */
|
||||
"", /* GPIO26 */
|
||||
"GPIO27",
|
||||
"GPIO28",
|
||||
"GPIO29",
|
||||
"GPIO30",
|
||||
"GPIO31",
|
||||
"", /* GPIO32 */
|
||||
"", /* GPIO33 */
|
||||
"", /* GPIO34 */
|
||||
"", /* GPIO35 */
|
||||
"", /* GPIO36 */
|
||||
"", /* GPIO37 */
|
||||
"", /* GPIO38 */
|
||||
"", /* GPIO39 */
|
||||
"PWM0_OUT",
|
||||
"NC", /* GPIO41 */
|
||||
"NC", /* GPIO42 */
|
||||
"NC", /* GPIO43 */
|
||||
"NC", /* GPIO44 */
|
||||
"", /* GPIO41 */
|
||||
"", /* GPIO42 */
|
||||
"", /* GPIO43 */
|
||||
"", /* GPIO44 */
|
||||
"PWM1_OUT",
|
||||
"HDMI_HPD_P",
|
||||
"SD_CARD_DET",
|
||||
|
|
|
|||
|
|
@ -13,7 +13,6 @@
|
|||
* This is based on the official GPU firmware DT blob.
|
||||
*
|
||||
* Legend:
|
||||
* "NC" = not connected (no rail from the SoC)
|
||||
* "FOO" = GPIO line named "FOO" on the schematic
|
||||
* "FOO_N" = GPIO line named "FOO" on schematic, active low
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -39,7 +39,6 @@
|
|||
* This is based on the official GPU firmware DT blob.
|
||||
*
|
||||
* Legend:
|
||||
* "NC" = not connected (no rail from the SoC)
|
||||
* "FOO" = GPIO line named "FOO" on the schematic
|
||||
* "FOO_N" = GPIO line named "FOO" on schematic, active low
|
||||
*/
|
||||
|
|
@ -74,19 +73,21 @@
|
|||
"GPIO27",
|
||||
"SDA0",
|
||||
"SCL0",
|
||||
"NC", /* GPIO30 */
|
||||
"NC", /* GPIO31 */
|
||||
"NC", /* GPIO32 */
|
||||
"NC", /* GPIO33 */
|
||||
"NC", /* GPIO34 */
|
||||
"NC", /* GPIO35 */
|
||||
"NC", /* GPIO36 */
|
||||
"NC", /* GPIO37 */
|
||||
"NC", /* GPIO38 */
|
||||
"NC", /* GPIO39 */
|
||||
/* Used by BT module */
|
||||
"CTS0",
|
||||
"RTS0",
|
||||
"TXD0",
|
||||
"RXD0",
|
||||
/* Used by Wifi */
|
||||
"SD1_CLK",
|
||||
"SD1_CMD",
|
||||
"SD1_DATA0",
|
||||
"SD1_DATA1",
|
||||
"SD1_DATA2",
|
||||
"SD1_DATA3",
|
||||
"CAM_GPIO1", /* GPIO40 */
|
||||
"WL_ON", /* GPIO41 */
|
||||
"NC", /* GPIO42 */
|
||||
"", /* GPIO42 */
|
||||
"WIFI_CLK", /* GPIO43 */
|
||||
"CAM_GPIO0", /* GPIO44 */
|
||||
"BT_ON", /* GPIO45 */
|
||||
|
|
|
|||
|
|
@ -29,7 +29,6 @@
|
|||
* This is based on the official GPU firmware DT blob.
|
||||
*
|
||||
* Legend:
|
||||
* "NC" = not connected (no rail from the SoC)
|
||||
* "FOO" = GPIO line named "FOO" on the schematic
|
||||
* "FOO_N" = GPIO line named "FOO" on schematic, active low
|
||||
*/
|
||||
|
|
@ -64,22 +63,22 @@
|
|||
"GPIO27",
|
||||
"SDA0",
|
||||
"SCL0",
|
||||
"NC", /* GPIO30 */
|
||||
"NC", /* GPIO31 */
|
||||
"", /* GPIO30 */
|
||||
"", /* GPIO31 */
|
||||
"CAM_GPIO1", /* GPIO32 */
|
||||
"NC", /* GPIO33 */
|
||||
"NC", /* GPIO34 */
|
||||
"NC", /* GPIO35 */
|
||||
"NC", /* GPIO36 */
|
||||
"NC", /* GPIO37 */
|
||||
"NC", /* GPIO38 */
|
||||
"NC", /* GPIO39 */
|
||||
"NC", /* GPIO40 */
|
||||
"", /* GPIO33 */
|
||||
"", /* GPIO34 */
|
||||
"", /* GPIO35 */
|
||||
"", /* GPIO36 */
|
||||
"", /* GPIO37 */
|
||||
"", /* GPIO38 */
|
||||
"", /* GPIO39 */
|
||||
"", /* GPIO40 */
|
||||
"CAM_GPIO0", /* GPIO41 */
|
||||
"NC", /* GPIO42 */
|
||||
"NC", /* GPIO43 */
|
||||
"NC", /* GPIO44 */
|
||||
"NC", /* GPIO45 */
|
||||
"", /* GPIO42 */
|
||||
"", /* GPIO43 */
|
||||
"", /* GPIO44 */
|
||||
"", /* GPIO45 */
|
||||
"HDMI_HPD_N",
|
||||
"STATUS_LED_N",
|
||||
/* Used by SD Card */
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue