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iommu/mediatek: Improve comment for the current region/bank 

No functional change. Just add more comment about the current region/bank
in the code.

Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230411093144.2690-4-yong.wu@mediatek.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
This commit is contained in:
Yong Wu 2023-04-11 17:31:33 +08:00 committed by Joerg Roedel
parent 559549b1f2
commit ae6693453a
1 changed files with 26 additions and 5 deletions
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31
drivers/iommu/mtk_iommu.c
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@ -197,12 +197,33 @@ struct mtk_iommu_plat_data {
char *pericfg_comp_str;
struct list_head *hw_list;
unsigned int iova_region_nr;
const struct mtk_iommu_iova_region *iova_region;
u8 banks_num;
bool banks_enable[MTK_IOMMU_BANK_MAX];
unsigned int banks_portmsk[MTK_IOMMU_BANK_MAX];
/*
* The IOMMU HW may support 16GB iova. In order to balance the IOVA ranges,
* different masters will be put in different iova ranges, for example vcodec
* is in 4G-8G and cam is in 8G-12G. Meanwhile, some masters may have the
* special IOVA range requirement, like CCU can only support the address
* 0x40000000-0x44000000.
* Here list the iova ranges this SoC supports and which larbs/ports are in
* which region.
*
* 16GB iova all use one pgtable, but each a region is a iommu group.
*/
struct {
unsigned int iova_region_nr;
const struct mtk_iommu_iova_region *iova_region;
};
/*
* The IOMMU HW may have 5 banks. Each bank has a independent pgtable.
* Here list how many banks this SoC supports/enables and which ports are in which bank.
*/
struct {
u8 banks_num;
bool banks_enable[MTK_IOMMU_BANK_MAX];
unsigned int banks_portmsk[MTK_IOMMU_BANK_MAX];
};
unsigned char larbid_remap[MTK_LARB_COM_MAX][MTK_LARB_SUBCOM_MAX];
};