drm/amdgpu/powerplay: Remove deprecated smc_read_arg
The new interface reads the argument in the call to send the message, so this is no longer needed, and shouldn't be used for concurrency safety reasons. Signed-off-by: Matt Coffin <mcoffin13@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -2302,7 +2302,6 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
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.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
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.system_features_control = smu_v11_0_system_features_control,
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.send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
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.read_smc_arg = smu_v11_0_read_arg,
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.init_display_count = smu_v11_0_init_display_count,
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.set_allowed_mask = smu_v11_0_set_allowed_mask,
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.get_enabled_mask = smu_v11_0_get_enabled_mask,
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@ -515,7 +515,6 @@ struct pptable_funcs {
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int (*system_features_control)(struct smu_context *smu, bool en);
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int (*send_smc_msg_with_param)(struct smu_context *smu,
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enum smu_message_type msg, uint32_t param, uint32_t *read_arg);
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int (*read_smc_arg)(struct smu_context *smu, uint32_t *arg);
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int (*init_display_count)(struct smu_context *smu, uint32_t count);
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int (*set_allowed_mask)(struct smu_context *smu);
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int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
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@ -138,8 +138,6 @@ enum smu_v11_0_baco_seq {
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BACO_SEQ_COUNT,
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};
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int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg);
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int smu_v11_0_init_microcode(struct smu_context *smu);
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int smu_v11_0_load_microcode(struct smu_context *smu);
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@ -40,8 +40,6 @@ struct smu_12_0_cmn2aisc_mapping {
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int smu_v12_0_send_msg_without_waiting(struct smu_context *smu,
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uint16_t msg);
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int smu_v12_0_read_arg(struct smu_context *smu, uint32_t *arg);
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int smu_v12_0_wait_for_response(struct smu_context *smu);
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int
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@ -2338,7 +2338,6 @@ static const struct pptable_funcs navi10_ppt_funcs = {
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.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
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.system_features_control = smu_v11_0_system_features_control,
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.send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
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.read_smc_arg = smu_v11_0_read_arg,
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.init_display_count = smu_v11_0_init_display_count,
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.set_allowed_mask = smu_v11_0_set_allowed_mask,
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.get_enabled_mask = smu_v11_0_get_enabled_mask,
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@ -917,7 +917,6 @@ static const struct pptable_funcs renoir_ppt_funcs = {
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.powergate_vcn = smu_v12_0_powergate_vcn,
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.powergate_jpeg = smu_v12_0_powergate_jpeg,
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.send_smc_msg_with_param = smu_v12_0_send_msg_with_param,
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.read_smc_arg = smu_v12_0_read_arg,
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.set_gfx_cgpg = smu_v12_0_set_gfx_cgpg,
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.gfx_off_control = smu_v12_0_gfx_off_control,
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.init_smc_tables = smu_v12_0_init_smc_tables,
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@ -86,8 +86,6 @@ static inline int smu_send_smc_msg(struct smu_context *smu, enum smu_message_typ
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return smu_send_smc_msg_with_param(smu, msg, 0, read_arg);
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}
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#define smu_read_smc_arg(smu, arg) \
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((smu)->ppt_funcs->read_smc_arg? (smu)->ppt_funcs->read_smc_arg((smu), (arg)) : 0)
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#define smu_alloc_dpm_context(smu) \
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((smu)->ppt_funcs->alloc_dpm_context ? (smu)->ppt_funcs->alloc_dpm_context((smu)) : 0)
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#define smu_init_display_count(smu, count) \
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@ -64,7 +64,7 @@ static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
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return 0;
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}
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int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
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static int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
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{
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struct amdgpu_device *adev = smu->adev;
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@ -50,7 +50,7 @@ int smu_v12_0_send_msg_without_waiting(struct smu_context *smu,
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return 0;
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}
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int smu_v12_0_read_arg(struct smu_context *smu, uint32_t *arg)
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static int smu_v12_0_read_arg(struct smu_context *smu, uint32_t *arg)
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{
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struct amdgpu_device *adev = smu->adev;
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@ -3243,7 +3243,6 @@ static const struct pptable_funcs vega20_ppt_funcs = {
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.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
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.system_features_control = smu_v11_0_system_features_control,
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.send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
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.read_smc_arg = smu_v11_0_read_arg,
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.init_display_count = smu_v11_0_init_display_count,
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.set_allowed_mask = smu_v11_0_set_allowed_mask,
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.get_enabled_mask = smu_v11_0_get_enabled_mask,
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