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iommu/amd: Process all IVHDs before enabling IOMMU features 

The ACPI IVRS table can contain multiple IVHD blocks. Each block contains
information used to initialize each IOMMU instance.

Currently, init_iommu_all sequentially process IVHD block and initialize
IOMMU instance one-by-one. However, certain features require all IOMMUs
to be configured in the same way system-wide. In case certain IVHD blocks
contain inconsistent information (most likely FW bugs), the driver needs
to go through and try to revert settings on IOMMUs that have already been
configured.

A solution is to split IOMMU initialization into 3 phases:

Phase1 : Processes information of the IVRS table for all IOMMU instances.
This allow all IVHDs to be processed prior to enabling features.

Phase2 : Early feature support check on all IOMMUs (using information in
IVHD blocks.

Phase3 : Iterates through all IOMMU instances and enabling features.

Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Link: https://lore.kernel.org/r/20220713225651.20758-5-suravee.suthikulpanit@amd.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
This commit is contained in:
Suravee Suthikulpanit 2022-07-13 17:56:46 -05:00 committed by Joerg Roedel
parent 9dd299d8c6
commit ae180ba426
1 changed files with 19 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
drivers/iommu/amd/init.c
View File

@ -1721,7 +1721,6 @@ static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h,
struct acpi_table_header *ivrs_base) struct acpi_table_header *ivrs_base)
{ {
struct amd_iommu_pci_seg *pci_seg; struct amd_iommu_pci_seg *pci_seg;
int ret;
pci_seg = get_pci_segment(h->pci_seg, ivrs_base); pci_seg = get_pci_segment(h->pci_seg, ivrs_base);
if (pci_seg == NULL) if (pci_seg == NULL)
@ -1802,6 +1801,13 @@ static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h,
if (!iommu->mmio_base) if (!iommu->mmio_base)
return -ENOMEM; return -ENOMEM;
return init_iommu_from_acpi(iommu, h);
}
static int __init init_iommu_one_late(struct amd_iommu *iommu)
{
int ret;
if (alloc_cwwb_sem(iommu)) if (alloc_cwwb_sem(iommu))
return -ENOMEM; return -ENOMEM;
@ -1823,10 +1829,6 @@ static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h,
if (amd_iommu_pre_enabled) if (amd_iommu_pre_enabled)
amd_iommu_pre_enabled = translation_pre_enabled(iommu); amd_iommu_pre_enabled = translation_pre_enabled(iommu);
ret = init_iommu_from_acpi(iommu, h);
if (ret)
return ret;
if (amd_iommu_irq_remap) { if (amd_iommu_irq_remap) {
ret = amd_iommu_create_irq_domain(iommu); ret = amd_iommu_create_irq_domain(iommu);
if (ret) if (ret)
@ -1837,7 +1839,7 @@ static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h,
* Make sure IOMMU is not considered to translate itself. The IVRS * Make sure IOMMU is not considered to translate itself. The IVRS
* table tells us so, but this is a lie! * table tells us so, but this is a lie!
*/ */
pci_seg->rlookup_table[iommu->devid] = NULL; iommu->pci_seg->rlookup_table[iommu->devid] = NULL;
return 0; return 0;
} }
@ -1882,6 +1884,7 @@ static int __init init_iommu_all(struct acpi_table_header *table)
end += table->length; end += table->length;
p += IVRS_HEADER_LENGTH; p += IVRS_HEADER_LENGTH;
/* Phase 1: Process all IVHD blocks */
while (p < end) { while (p < end) {
h = (struct ivhd_header *)p; h = (struct ivhd_header *)p;
if (*p == amd_iommu_target_ivhd_type) { if (*p == amd_iommu_target_ivhd_type) {
@ -1907,6 +1910,16 @@ static int __init init_iommu_all(struct acpi_table_header *table)
} }
WARN_ON(p != end); WARN_ON(p != end);
/* Phase 2 : Early feature support check */
get_global_efr();
/* Phase 3 : Enabling IOMMU features */
for_each_iommu(iommu) {
ret = init_iommu_one_late(iommu);
if (ret)
return ret;
}
return 0; return 0;
} }