clk: stm32mp13: add all STM32MP13 peripheral clocks
All peripheral clocks are mainly based on stm32_gate clock. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Link: https://lore.kernel.org/r/20220516070600.7692-9-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Gabriel Fernandez
Stephen Boyd
parent
93e336c2d6
commit
ae0da9a6db
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@ -537,6 +537,303 @@ static const char * const mco2_src[] = {
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"ck_mpu", "ck_axi", "ck_mlahb", "pll4_p", "ck_hse", "ck_hsi"
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};
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/* Timer clocks */
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static struct clk_stm32_gate tim2_k = {
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.gate_id = GATE_TIM2,
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.hw.init = CLK_HW_INIT("tim2_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
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};
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static struct clk_stm32_gate tim3_k = {
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.gate_id = GATE_TIM3,
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.hw.init = CLK_HW_INIT("tim3_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
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};
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static struct clk_stm32_gate tim4_k = {
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.gate_id = GATE_TIM4,
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.hw.init = CLK_HW_INIT("tim4_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
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};
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static struct clk_stm32_gate tim5_k = {
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.gate_id = GATE_TIM5,
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.hw.init = CLK_HW_INIT("tim5_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
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};
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static struct clk_stm32_gate tim6_k = {
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.gate_id = GATE_TIM6,
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.hw.init = CLK_HW_INIT("tim6_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
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};
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static struct clk_stm32_gate tim7_k = {
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.gate_id = GATE_TIM7,
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.hw.init = CLK_HW_INIT("tim7_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
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};
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static struct clk_stm32_gate tim1_k = {
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.gate_id = GATE_TIM1,
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.hw.init = CLK_HW_INIT("tim1_k", "timg2_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
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};
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static struct clk_stm32_gate tim8_k = {
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.gate_id = GATE_TIM8,
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.hw.init = CLK_HW_INIT("tim8_k", "timg2_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
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};
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static struct clk_stm32_gate tim12_k = {
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.gate_id = GATE_TIM12,
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.hw.init = CLK_HW_INIT("tim12_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
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};
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static struct clk_stm32_gate tim13_k = {
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.gate_id = GATE_TIM13,
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.hw.init = CLK_HW_INIT("tim13_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
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};
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static struct clk_stm32_gate tim14_k = {
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.gate_id = GATE_TIM14,
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.hw.init = CLK_HW_INIT("tim14_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
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};
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static struct clk_stm32_gate tim15_k = {
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.gate_id = GATE_TIM15,
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.hw.init = CLK_HW_INIT("tim15_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
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};
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static struct clk_stm32_gate tim16_k = {
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.gate_id = GATE_TIM16,
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.hw.init = CLK_HW_INIT("tim16_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
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};
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static struct clk_stm32_gate tim17_k = {
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.gate_id = GATE_TIM17,
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.hw.init = CLK_HW_INIT("tim17_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
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};
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/* Peripheral clocks */
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static struct clk_stm32_gate sai1 = {
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.gate_id = GATE_SAI1,
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.hw.init = CLK_HW_INIT("sai1", "pclk2", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate sai2 = {
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.gate_id = GATE_SAI2,
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.hw.init = CLK_HW_INIT("sai2", "pclk2", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate syscfg = {
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.gate_id = GATE_SYSCFG,
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.hw.init = CLK_HW_INIT("syscfg", "pclk3", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate vref = {
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.gate_id = GATE_VREF,
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.hw.init = CLK_HW_INIT("vref", "pclk3", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate dts = {
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.gate_id = GATE_DTS,
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.hw.init = CLK_HW_INIT("dts", "pclk3", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate pmbctrl = {
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.gate_id = GATE_PMBCTRL,
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.hw.init = CLK_HW_INIT("pmbctrl", "pclk3", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate hdp = {
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.gate_id = GATE_HDP,
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.hw.init = CLK_HW_INIT("hdp", "pclk3", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate iwdg2 = {
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.gate_id = GATE_IWDG2APB,
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.hw.init = CLK_HW_INIT("iwdg2", "pclk4", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate stgenro = {
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.gate_id = GATE_STGENRO,
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.hw.init = CLK_HW_INIT("stgenro", "pclk4", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate gpioa = {
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.gate_id = GATE_GPIOA,
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.hw.init = CLK_HW_INIT("gpioa", "pclk4", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate gpiob = {
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.gate_id = GATE_GPIOB,
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.hw.init = CLK_HW_INIT("gpiob", "pclk4", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate gpioc = {
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.gate_id = GATE_GPIOC,
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.hw.init = CLK_HW_INIT("gpioc", "pclk4", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate gpiod = {
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.gate_id = GATE_GPIOD,
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.hw.init = CLK_HW_INIT("gpiod", "pclk4", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate gpioe = {
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.gate_id = GATE_GPIOE,
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.hw.init = CLK_HW_INIT("gpioe", "pclk4", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate gpiof = {
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.gate_id = GATE_GPIOF,
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.hw.init = CLK_HW_INIT("gpiof", "pclk4", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate gpiog = {
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.gate_id = GATE_GPIOG,
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.hw.init = CLK_HW_INIT("gpiog", "pclk4", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate gpioh = {
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.gate_id = GATE_GPIOH,
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.hw.init = CLK_HW_INIT("gpioh", "pclk4", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate gpioi = {
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.gate_id = GATE_GPIOI,
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.hw.init = CLK_HW_INIT("gpioi", "pclk4", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate tsc = {
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.gate_id = GATE_TSC,
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.hw.init = CLK_HW_INIT("tsc", "pclk4", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate ddrperfm = {
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.gate_id = GATE_DDRPERFM,
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.hw.init = CLK_HW_INIT("ddrperfm", "pclk4", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate tzpc = {
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.gate_id = GATE_TZC,
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.hw.init = CLK_HW_INIT("tzpc", "pclk5", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate iwdg1 = {
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.gate_id = GATE_IWDG1APB,
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.hw.init = CLK_HW_INIT("iwdg1", "pclk5", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate bsec = {
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.gate_id = GATE_BSEC,
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.hw.init = CLK_HW_INIT("bsec", "pclk5", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate dma1 = {
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.gate_id = GATE_DMA1,
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.hw.init = CLK_HW_INIT("dma1", "ck_mlahb", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate dma2 = {
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.gate_id = GATE_DMA2,
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.hw.init = CLK_HW_INIT("dma2", "ck_mlahb", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate dmamux1 = {
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.gate_id = GATE_DMAMUX1,
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.hw.init = CLK_HW_INIT("dmamux1", "ck_mlahb", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate dma3 = {
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.gate_id = GATE_DMA3,
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.hw.init = CLK_HW_INIT("dma3", "ck_mlahb", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate dmamux2 = {
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.gate_id = GATE_DMAMUX2,
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.hw.init = CLK_HW_INIT("dmamux2", "ck_mlahb", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate adc1 = {
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.gate_id = GATE_ADC1,
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.hw.init = CLK_HW_INIT("adc1", "ck_mlahb", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate adc2 = {
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.gate_id = GATE_ADC2,
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.hw.init = CLK_HW_INIT("adc2", "ck_mlahb", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate pka = {
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.gate_id = GATE_PKA,
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.hw.init = CLK_HW_INIT("pka", "ck_axi", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate cryp1 = {
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.gate_id = GATE_CRYP1,
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.hw.init = CLK_HW_INIT("cryp1", "ck_axi", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate hash1 = {
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.gate_id = GATE_HASH1,
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.hw.init = CLK_HW_INIT("hash1", "ck_axi", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate bkpsram = {
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.gate_id = GATE_BKPSRAM,
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.hw.init = CLK_HW_INIT("bkpsram", "ck_axi", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate mdma = {
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.gate_id = GATE_MDMA,
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.hw.init = CLK_HW_INIT("mdma", "ck_axi", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate eth1tx = {
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.gate_id = GATE_ETH1TX,
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.hw.init = CLK_HW_INIT("eth1tx", "ck_axi", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate eth1rx = {
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.gate_id = GATE_ETH1RX,
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.hw.init = CLK_HW_INIT("eth1rx", "ck_axi", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate eth1mac = {
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.gate_id = GATE_ETH1MAC,
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.hw.init = CLK_HW_INIT("eth1mac", "ck_axi", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate eth2tx = {
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.gate_id = GATE_ETH2TX,
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.hw.init = CLK_HW_INIT("eth2tx", "ck_axi", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate eth2rx = {
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.gate_id = GATE_ETH2RX,
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.hw.init = CLK_HW_INIT("eth2rx", "ck_axi", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate eth2mac = {
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.gate_id = GATE_ETH2MAC,
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.hw.init = CLK_HW_INIT("eth2mac", "ck_axi", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate crc1 = {
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.gate_id = GATE_CRC1,
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.hw.init = CLK_HW_INIT("crc1", "ck_axi", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate usbh = {
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.gate_id = GATE_USBH,
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.hw.init = CLK_HW_INIT("usbh", "ck_axi", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate eth1stp = {
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.gate_id = GATE_ETH1STP,
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.hw.init = CLK_HW_INIT("eth1stp", "ck_axi", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_gate eth2stp = {
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.gate_id = GATE_ETH2STP,
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.hw.init = CLK_HW_INIT("eth2stp", "ck_axi", &clk_stm32_gate_ops, 0),
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};
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static struct clk_stm32_mux ck_ker_eth1 = {
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.mux_id = MUX_ETH1,
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.hw.init = CLK_HW_INIT_PARENTS("ck_ker_eth1", eth12_src, &clk_stm32_mux_ops,
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@ -573,6 +870,69 @@ static struct clk_stm32_composite ck_mco2 = {
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};
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static const struct clock_config stm32mp13_clock_cfg[] = {
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/* Timer clocks */
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STM32_GATE_CFG(TIM2_K, tim2_k, SECF_NONE),
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STM32_GATE_CFG(TIM3_K, tim3_k, SECF_NONE),
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STM32_GATE_CFG(TIM4_K, tim4_k, SECF_NONE),
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STM32_GATE_CFG(TIM5_K, tim5_k, SECF_NONE),
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STM32_GATE_CFG(TIM6_K, tim6_k, SECF_NONE),
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STM32_GATE_CFG(TIM7_K, tim7_k, SECF_NONE),
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STM32_GATE_CFG(TIM1_K, tim1_k, SECF_NONE),
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STM32_GATE_CFG(TIM8_K, tim8_k, SECF_NONE),
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STM32_GATE_CFG(TIM12_K, tim12_k, SECF_TIM12),
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STM32_GATE_CFG(TIM13_K, tim13_k, SECF_TIM13),
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STM32_GATE_CFG(TIM14_K, tim14_k, SECF_TIM14),
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STM32_GATE_CFG(TIM15_K, tim15_k, SECF_TIM15),
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STM32_GATE_CFG(TIM16_K, tim16_k, SECF_TIM16),
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STM32_GATE_CFG(TIM17_K, tim17_k, SECF_TIM17),
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/* Peripheral clocks */
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STM32_GATE_CFG(SAI1, sai1, SECF_NONE),
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STM32_GATE_CFG(SAI2, sai2, SECF_NONE),
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STM32_GATE_CFG(SYSCFG, syscfg, SECF_NONE),
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STM32_GATE_CFG(VREF, vref, SECF_VREF),
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STM32_GATE_CFG(DTS, dts, SECF_NONE),
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STM32_GATE_CFG(PMBCTRL, pmbctrl, SECF_NONE),
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STM32_GATE_CFG(HDP, hdp, SECF_NONE),
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STM32_GATE_CFG(IWDG2, iwdg2, SECF_NONE),
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STM32_GATE_CFG(STGENRO, stgenro, SECF_STGENRO),
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STM32_GATE_CFG(TZPC, tzpc, SECF_TZC),
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STM32_GATE_CFG(IWDG1, iwdg1, SECF_IWDG1),
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STM32_GATE_CFG(BSEC, bsec, SECF_BSEC),
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STM32_GATE_CFG(DMA1, dma1, SECF_NONE),
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STM32_GATE_CFG(DMA2, dma2, SECF_NONE),
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STM32_GATE_CFG(DMAMUX1, dmamux1, SECF_NONE),
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STM32_GATE_CFG(DMA3, dma3, SECF_DMA3),
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STM32_GATE_CFG(DMAMUX2, dmamux2, SECF_DMAMUX2),
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STM32_GATE_CFG(ADC1, adc1, SECF_ADC1),
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STM32_GATE_CFG(ADC2, adc2, SECF_ADC2),
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STM32_GATE_CFG(GPIOA, gpioa, SECF_NONE),
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STM32_GATE_CFG(GPIOB, gpiob, SECF_NONE),
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STM32_GATE_CFG(GPIOC, gpioc, SECF_NONE),
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STM32_GATE_CFG(GPIOD, gpiod, SECF_NONE),
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STM32_GATE_CFG(GPIOE, gpioe, SECF_NONE),
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STM32_GATE_CFG(GPIOF, gpiof, SECF_NONE),
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STM32_GATE_CFG(GPIOG, gpiog, SECF_NONE),
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STM32_GATE_CFG(GPIOH, gpioh, SECF_NONE),
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STM32_GATE_CFG(GPIOI, gpioi, SECF_NONE),
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STM32_GATE_CFG(TSC, tsc, SECF_TZC),
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STM32_GATE_CFG(PKA, pka, SECF_PKA),
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STM32_GATE_CFG(CRYP1, cryp1, SECF_CRYP1),
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STM32_GATE_CFG(HASH1, hash1, SECF_HASH1),
|
||||
STM32_GATE_CFG(BKPSRAM, bkpsram, SECF_BKPSRAM),
|
||||
STM32_GATE_CFG(MDMA, mdma, SECF_NONE),
|
||||
STM32_GATE_CFG(ETH1TX, eth1tx, SECF_ETH1TX),
|
||||
STM32_GATE_CFG(ETH1RX, eth1rx, SECF_ETH1RX),
|
||||
STM32_GATE_CFG(ETH1MAC, eth1mac, SECF_ETH1MAC),
|
||||
STM32_GATE_CFG(ETH2TX, eth2tx, SECF_ETH2TX),
|
||||
STM32_GATE_CFG(ETH2RX, eth2rx, SECF_ETH2RX),
|
||||
STM32_GATE_CFG(ETH2MAC, eth2mac, SECF_ETH2MAC),
|
||||
STM32_GATE_CFG(CRC1, crc1, SECF_NONE),
|
||||
STM32_GATE_CFG(USBH, usbh, SECF_NONE),
|
||||
STM32_GATE_CFG(DDRPERFM, ddrperfm, SECF_NONE),
|
||||
STM32_GATE_CFG(ETH1STP, eth1stp, SECF_ETH1STP),
|
||||
STM32_GATE_CFG(ETH2STP, eth2stp, SECF_ETH2STP),
|
||||
|
||||
STM32_MUX_CFG(NO_ID, ck_ker_eth1, SECF_ETH1CK),
|
||||
STM32_GATE_CFG(ETH1CK_K, eth1ck_k, SECF_ETH1CK),
|
||||
STM32_DIV_CFG(ETH1PTP_K, eth1ptp_k, SECF_ETH1CK),
|
||||
|
|
|
|||
Loading…
Reference in New Issue