spi: mediatek: fix spi clock usage error
spi clock manages flow: CLK_TOP_SYSPLL3_D2 ---> CLK_TOP_SPI_SEL ---> CLK_PERI_SPI0 (source clock) (clock mux) (clock gate) spi driver should choose source clock by clock mux, then enable clock gate. Signed-off-by: Leilk Liu <leilk.liu@mediatek.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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ca9f26a279
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adcbcfea15
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@ -85,7 +85,7 @@ struct mtk_spi {
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void __iomem *base;
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u32 state;
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u32 pad_sel;
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struct clk *spi_clk, *parent_clk;
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struct clk *parent_clk, *sel_clk, *spi_clk;
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struct spi_transfer *cur_transfer;
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u32 xfer_len;
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struct scatterlist *tx_sgl, *rx_sgl;
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@ -576,13 +576,6 @@ static int mtk_spi_probe(struct platform_device *pdev)
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goto err_put_master;
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}
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mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk");
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if (IS_ERR(mdata->spi_clk)) {
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ret = PTR_ERR(mdata->spi_clk);
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dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret);
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goto err_put_master;
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}
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mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk");
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if (IS_ERR(mdata->parent_clk)) {
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ret = PTR_ERR(mdata->parent_clk);
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@ -590,13 +583,27 @@ static int mtk_spi_probe(struct platform_device *pdev)
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goto err_put_master;
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}
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mdata->sel_clk = devm_clk_get(&pdev->dev, "sel-clk");
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if (IS_ERR(mdata->sel_clk)) {
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ret = PTR_ERR(mdata->spi_clk);
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dev_err(&pdev->dev, "failed to get sel-clk: %d\n", ret);
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goto err_put_master;
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}
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mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk");
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if (IS_ERR(mdata->spi_clk)) {
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ret = PTR_ERR(mdata->parent_clk);
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dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret);
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goto err_put_master;
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}
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ret = clk_prepare_enable(mdata->spi_clk);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret);
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goto err_put_master;
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}
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ret = clk_set_parent(mdata->spi_clk, mdata->parent_clk);
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ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
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goto err_disable_clk;
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