ARM: dts: r8a7778: Add HSCIF0/1 support
Add HSCIF0/1 clocks and device nodes, based on Rev. 1.00 of the R-Car M1A datasheet. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> [geert: Squashed two patches] [geert: Correct HSCIF1 module clock index] [geert: Correct reg properties for non-LPAE] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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@ -367,6 +367,30 @@
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status = "disabled";
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};
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hscif0: serial@ffe48000 {
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compatible = "renesas,hscif-r8a7778",
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"renesas,rcar-gen1-hscif", "renesas,hscif";
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reg = <0xffe48000 96>;
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interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7778_CLK_HSCIF0>,
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<&cpg_clocks R8A7778_CLK_S>, <&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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hscif1: serial@ffe49000 {
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compatible = "renesas,hscif-r8a7778",
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"renesas,rcar-gen1-hscif", "renesas,hscif";
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reg = <0xffe49000 96>;
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interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7778_CLK_HSCIF1>,
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<&cpg_clocks R8A7778_CLK_S>, <&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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mmcif: mmc@ffe4e000 {
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compatible = "renesas,mmcif-r8a7778", "renesas,sh-mmcif";
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reg = <0xffe4e000 0x100>;
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@ -535,6 +559,8 @@
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_S>,
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<&cpg_clocks R8A7778_CLK_S>,
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>,
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@ -551,6 +577,7 @@
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R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1
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R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3
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R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5
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R8A7778_CLK_HSCIF0 R8A7778_CLK_HSCIF1
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R8A7778_CLK_TMU0 R8A7778_CLK_TMU1
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R8A7778_CLK_TMU2 R8A7778_CLK_SSI0
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R8A7778_CLK_SSI1 R8A7778_CLK_SSI2
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@ -560,6 +587,7 @@
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clock-output-names =
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"i2c0", "i2c1", "i2c2", "i2c3", "scif0",
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"scif1", "scif2", "scif3", "scif4", "scif5",
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"hscif0", "hscif1",
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"tmu0", "tmu1", "tmu2", "ssi0", "ssi1",
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"ssi2", "ssi3", "sru", "hspi";
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};
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@ -30,6 +30,8 @@
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#define R8A7778_CLK_SCIF3 23
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#define R8A7778_CLK_SCIF4 22
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#define R8A7778_CLK_SCIF5 21
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#define R8A7778_CLK_HSCIF0 19
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#define R8A7778_CLK_HSCIF1 18
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#define R8A7778_CLK_TMU0 16
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#define R8A7778_CLK_TMU1 15
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#define R8A7778_CLK_TMU2 14
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