Merge branch 'perf/x86-ibs' into perf/core
This commit is contained in:
Ingo Molnar
commit
ad8537cda6
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@ -134,6 +134,8 @@
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#define MSR_AMD64_IBSFETCHCTL 0xc0011030
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#define MSR_AMD64_IBSFETCHLINAD 0xc0011031
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#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
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#define MSR_AMD64_IBSFETCH_REG_COUNT 3
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#define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
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#define MSR_AMD64_IBSOPCTL 0xc0011033
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#define MSR_AMD64_IBSOPRIP 0xc0011034
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#define MSR_AMD64_IBSOPDATA 0xc0011035
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@ -141,8 +143,11 @@
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#define MSR_AMD64_IBSOPDATA3 0xc0011037
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#define MSR_AMD64_IBSDCLINAD 0xc0011038
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#define MSR_AMD64_IBSDCPHYSAD 0xc0011039
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#define MSR_AMD64_IBSOP_REG_COUNT 7
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#define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
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#define MSR_AMD64_IBSCTL 0xc001103a
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#define MSR_AMD64_IBSBRTARGET 0xc001103b
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#define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */
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/* Fam 15h MSRs */
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#define MSR_F15H_PERF_CTL 0xc0010200
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@ -178,6 +178,8 @@ struct x86_pmu_capability {
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#define IBS_FETCH_MAX_CNT 0x0000FFFFULL
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/* IbsOpCtl bits */
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/* lower 4 bits of the current count are ignored: */
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#define IBS_OP_CUR_CNT (0xFFFF0ULL<<32)
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#define IBS_OP_CNT_CTL (1ULL<<19)
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#define IBS_OP_VAL (1ULL<<18)
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#define IBS_OP_ENABLE (1ULL<<17)
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@ -16,36 +16,460 @@ static u32 ibs_caps;
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#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
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static struct pmu perf_ibs;
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#include <linux/kprobes.h>
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#include <linux/hardirq.h>
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#include <asm/nmi.h>
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#define IBS_FETCH_CONFIG_MASK (IBS_FETCH_RAND_EN | IBS_FETCH_MAX_CNT)
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#define IBS_OP_CONFIG_MASK IBS_OP_MAX_CNT
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enum ibs_states {
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IBS_ENABLED = 0,
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IBS_STARTED = 1,
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IBS_STOPPING = 2,
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IBS_MAX_STATES,
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};
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struct cpu_perf_ibs {
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struct perf_event *event;
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unsigned long state[BITS_TO_LONGS(IBS_MAX_STATES)];
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};
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struct perf_ibs {
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struct pmu pmu;
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unsigned int msr;
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u64 config_mask;
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u64 cnt_mask;
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u64 enable_mask;
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u64 valid_mask;
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u64 max_period;
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unsigned long offset_mask[1];
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int offset_max;
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struct cpu_perf_ibs __percpu *pcpu;
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u64 (*get_count)(u64 config);
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};
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struct perf_ibs_data {
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u32 size;
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union {
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u32 data[0]; /* data buffer starts here */
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u32 caps;
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};
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u64 regs[MSR_AMD64_IBS_REG_COUNT_MAX];
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};
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static int
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perf_event_set_period(struct hw_perf_event *hwc, u64 min, u64 max, u64 *count)
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{
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s64 left = local64_read(&hwc->period_left);
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s64 period = hwc->sample_period;
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int overflow = 0;
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/*
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* If we are way outside a reasonable range then just skip forward:
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*/
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if (unlikely(left <= -period)) {
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left = period;
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local64_set(&hwc->period_left, left);
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hwc->last_period = period;
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overflow = 1;
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}
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if (unlikely(left <= 0)) {
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left += period;
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local64_set(&hwc->period_left, left);
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hwc->last_period = period;
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overflow = 1;
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}
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if (unlikely(left < min))
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left = min;
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if (left > max)
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left = max;
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*count = (u64)left;
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return overflow;
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}
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static int
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perf_event_try_update(struct perf_event *event, u64 new_raw_count, int width)
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{
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struct hw_perf_event *hwc = &event->hw;
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int shift = 64 - width;
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u64 prev_raw_count;
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u64 delta;
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/*
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* Careful: an NMI might modify the previous event value.
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*
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* Our tactic to handle this is to first atomically read and
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* exchange a new raw count - then add that new-prev delta
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* count to the generic event atomically:
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*/
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prev_raw_count = local64_read(&hwc->prev_count);
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if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
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new_raw_count) != prev_raw_count)
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return 0;
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/*
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* Now we have the new raw value and have updated the prev
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* timestamp already. We can now calculate the elapsed delta
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* (event-)time and add that to the generic event.
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*
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* Careful, not all hw sign-extends above the physical width
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* of the count.
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*/
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delta = (new_raw_count << shift) - (prev_raw_count << shift);
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delta >>= shift;
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local64_add(delta, &event->count);
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local64_sub(delta, &hwc->period_left);
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return 1;
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}
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static struct perf_ibs perf_ibs_fetch;
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static struct perf_ibs perf_ibs_op;
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static struct perf_ibs *get_ibs_pmu(int type)
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{
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if (perf_ibs_fetch.pmu.type == type)
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return &perf_ibs_fetch;
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if (perf_ibs_op.pmu.type == type)
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return &perf_ibs_op;
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return NULL;
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}
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static int perf_ibs_init(struct perf_event *event)
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{
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if (perf_ibs.type != event->attr.type)
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struct hw_perf_event *hwc = &event->hw;
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struct perf_ibs *perf_ibs;
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u64 max_cnt, config;
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perf_ibs = get_ibs_pmu(event->attr.type);
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if (!perf_ibs)
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return -ENOENT;
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config = event->attr.config;
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if (config & ~perf_ibs->config_mask)
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return -EINVAL;
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if (hwc->sample_period) {
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if (config & perf_ibs->cnt_mask)
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/* raw max_cnt may not be set */
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return -EINVAL;
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if (hwc->sample_period & 0x0f)
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/* lower 4 bits can not be set in ibs max cnt */
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return -EINVAL;
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} else {
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max_cnt = config & perf_ibs->cnt_mask;
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config &= ~perf_ibs->cnt_mask;
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event->attr.sample_period = max_cnt << 4;
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hwc->sample_period = event->attr.sample_period;
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}
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if (!hwc->sample_period)
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return -EINVAL;
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hwc->config_base = perf_ibs->msr;
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hwc->config = config;
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return 0;
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}
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static int perf_ibs_set_period(struct perf_ibs *perf_ibs,
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struct hw_perf_event *hwc, u64 *period)
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{
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int ret;
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/* ignore lower 4 bits in min count: */
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ret = perf_event_set_period(hwc, 1<<4, perf_ibs->max_period, period);
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local64_set(&hwc->prev_count, 0);
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return ret;
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}
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static u64 get_ibs_fetch_count(u64 config)
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{
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return (config & IBS_FETCH_CNT) >> 12;
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}
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static u64 get_ibs_op_count(u64 config)
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{
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return (config & IBS_OP_CUR_CNT) >> 32;
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}
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static void
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perf_ibs_event_update(struct perf_ibs *perf_ibs, struct perf_event *event,
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u64 config)
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{
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u64 count = perf_ibs->get_count(config);
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while (!perf_event_try_update(event, count, 20)) {
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rdmsrl(event->hw.config_base, config);
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count = perf_ibs->get_count(config);
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}
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}
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/* Note: The enable mask must be encoded in the config argument. */
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static inline void perf_ibs_enable_event(struct hw_perf_event *hwc, u64 config)
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{
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wrmsrl(hwc->config_base, hwc->config | config);
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}
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/*
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* We cannot restore the ibs pmu state, so we always needs to update
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* the event while stopping it and then reset the state when starting
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* again. Thus, ignoring PERF_EF_RELOAD and PERF_EF_UPDATE flags in
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* perf_ibs_start()/perf_ibs_stop() and instead always do it.
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*/
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static void perf_ibs_start(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hwc = &event->hw;
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struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
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struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
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u64 config;
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if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
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return;
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WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
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hwc->state = 0;
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perf_ibs_set_period(perf_ibs, hwc, &config);
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config = (config >> 4) | perf_ibs->enable_mask;
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set_bit(IBS_STARTED, pcpu->state);
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perf_ibs_enable_event(hwc, config);
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perf_event_update_userpage(event);
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}
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static void perf_ibs_stop(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hwc = &event->hw;
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struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
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struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
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u64 val;
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int stopping;
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stopping = test_and_clear_bit(IBS_STARTED, pcpu->state);
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if (!stopping && (hwc->state & PERF_HES_UPTODATE))
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return;
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rdmsrl(hwc->config_base, val);
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if (stopping) {
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set_bit(IBS_STOPPING, pcpu->state);
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val &= ~perf_ibs->enable_mask;
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wrmsrl(hwc->config_base, val);
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WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
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hwc->state |= PERF_HES_STOPPED;
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}
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if (hwc->state & PERF_HES_UPTODATE)
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return;
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perf_ibs_event_update(perf_ibs, event, val);
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hwc->state |= PERF_HES_UPTODATE;
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}
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static int perf_ibs_add(struct perf_event *event, int flags)
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{
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struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
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struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
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if (test_and_set_bit(IBS_ENABLED, pcpu->state))
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return -ENOSPC;
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event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
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pcpu->event = event;
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if (flags & PERF_EF_START)
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perf_ibs_start(event, PERF_EF_RELOAD);
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return 0;
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}
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static void perf_ibs_del(struct perf_event *event, int flags)
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{
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struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
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struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
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if (!test_and_clear_bit(IBS_ENABLED, pcpu->state))
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return;
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perf_ibs_stop(event, PERF_EF_UPDATE);
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pcpu->event = NULL;
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perf_event_update_userpage(event);
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}
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static struct pmu perf_ibs = {
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.event_init= perf_ibs_init,
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.add= perf_ibs_add,
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.del= perf_ibs_del,
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static void perf_ibs_read(struct perf_event *event) { }
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static struct perf_ibs perf_ibs_fetch = {
|
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.pmu = {
|
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.task_ctx_nr = perf_invalid_context,
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.event_init = perf_ibs_init,
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.add = perf_ibs_add,
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.del = perf_ibs_del,
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.start = perf_ibs_start,
|
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.stop = perf_ibs_stop,
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.read = perf_ibs_read,
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},
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.msr = MSR_AMD64_IBSFETCHCTL,
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.config_mask = IBS_FETCH_CONFIG_MASK,
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.cnt_mask = IBS_FETCH_MAX_CNT,
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.enable_mask = IBS_FETCH_ENABLE,
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.valid_mask = IBS_FETCH_VAL,
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.max_period = IBS_FETCH_MAX_CNT << 4,
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.offset_mask = { MSR_AMD64_IBSFETCH_REG_MASK },
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.offset_max = MSR_AMD64_IBSFETCH_REG_COUNT,
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|
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.get_count = get_ibs_fetch_count,
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};
|
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|
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static struct perf_ibs perf_ibs_op = {
|
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.pmu = {
|
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.task_ctx_nr = perf_invalid_context,
|
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.event_init = perf_ibs_init,
|
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.add = perf_ibs_add,
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.del = perf_ibs_del,
|
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.start = perf_ibs_start,
|
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.stop = perf_ibs_stop,
|
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.read = perf_ibs_read,
|
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},
|
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.msr = MSR_AMD64_IBSOPCTL,
|
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.config_mask = IBS_OP_CONFIG_MASK,
|
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.cnt_mask = IBS_OP_MAX_CNT,
|
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.enable_mask = IBS_OP_ENABLE,
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.valid_mask = IBS_OP_VAL,
|
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.max_period = IBS_OP_MAX_CNT << 4,
|
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.offset_mask = { MSR_AMD64_IBSOP_REG_MASK },
|
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.offset_max = MSR_AMD64_IBSOP_REG_COUNT,
|
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|
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.get_count = get_ibs_op_count,
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};
|
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|
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static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)
|
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{
|
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struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
|
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struct perf_event *event = pcpu->event;
|
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struct hw_perf_event *hwc = &event->hw;
|
||||
struct perf_sample_data data;
|
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struct perf_raw_record raw;
|
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struct pt_regs regs;
|
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struct perf_ibs_data ibs_data;
|
||||
int offset, size, overflow, reenable;
|
||||
unsigned int msr;
|
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u64 *buf, config;
|
||||
|
||||
if (!test_bit(IBS_STARTED, pcpu->state)) {
|
||||
/* Catch spurious interrupts after stopping IBS: */
|
||||
if (!test_and_clear_bit(IBS_STOPPING, pcpu->state))
|
||||
return 0;
|
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rdmsrl(perf_ibs->msr, *ibs_data.regs);
|
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return (*ibs_data.regs & perf_ibs->valid_mask) ? 1 : 0;
|
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}
|
||||
|
||||
msr = hwc->config_base;
|
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buf = ibs_data.regs;
|
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rdmsrl(msr, *buf);
|
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if (!(*buf++ & perf_ibs->valid_mask))
|
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return 0;
|
||||
|
||||
perf_sample_data_init(&data, 0);
|
||||
if (event->attr.sample_type & PERF_SAMPLE_RAW) {
|
||||
ibs_data.caps = ibs_caps;
|
||||
size = 1;
|
||||
offset = 1;
|
||||
do {
|
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rdmsrl(msr + offset, *buf++);
|
||||
size++;
|
||||
offset = find_next_bit(perf_ibs->offset_mask,
|
||||
perf_ibs->offset_max,
|
||||
offset + 1);
|
||||
} while (offset < perf_ibs->offset_max);
|
||||
raw.size = sizeof(u32) + sizeof(u64) * size;
|
||||
raw.data = ibs_data.data;
|
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data.raw = &raw;
|
||||
}
|
||||
|
||||
regs = *iregs; /* XXX: update ip from ibs sample */
|
||||
|
||||
/*
|
||||
* Emulate IbsOpCurCnt in MSRC001_1033 (IbsOpCtl), not
|
||||
* supported in all cpus. As this triggered an interrupt, we
|
||||
* set the current count to the max count.
|
||||
*/
|
||||
config = ibs_data.regs[0];
|
||||
if (perf_ibs == &perf_ibs_op && !(ibs_caps & IBS_CAPS_RDWROPCNT)) {
|
||||
config &= ~IBS_OP_CUR_CNT;
|
||||
config |= (config & IBS_OP_MAX_CNT) << 36;
|
||||
}
|
||||
|
||||
perf_ibs_event_update(perf_ibs, event, config);
|
||||
|
||||
overflow = perf_ibs_set_period(perf_ibs, hwc, &config);
|
||||
reenable = !(overflow && perf_event_overflow(event, &data, ®s));
|
||||
config = (config >> 4) | (reenable ? perf_ibs->enable_mask : 0);
|
||||
perf_ibs_enable_event(hwc, config);
|
||||
|
||||
perf_event_update_userpage(event);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int __kprobes
|
||||
perf_ibs_nmi_handler(unsigned int cmd, struct pt_regs *regs)
|
||||
{
|
||||
int handled = 0;
|
||||
|
||||
handled += perf_ibs_handle_irq(&perf_ibs_fetch, regs);
|
||||
handled += perf_ibs_handle_irq(&perf_ibs_op, regs);
|
||||
|
||||
if (handled)
|
||||
inc_irq_stat(apic_perf_irqs);
|
||||
|
||||
return handled;
|
||||
}
|
||||
|
||||
static __init int perf_ibs_pmu_init(struct perf_ibs *perf_ibs, char *name)
|
||||
{
|
||||
struct cpu_perf_ibs __percpu *pcpu;
|
||||
int ret;
|
||||
|
||||
pcpu = alloc_percpu(struct cpu_perf_ibs);
|
||||
if (!pcpu)
|
||||
return -ENOMEM;
|
||||
|
||||
perf_ibs->pcpu = pcpu;
|
||||
|
||||
ret = perf_pmu_register(&perf_ibs->pmu, name, -1);
|
||||
if (ret) {
|
||||
perf_ibs->pcpu = NULL;
|
||||
free_percpu(pcpu);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static __init int perf_event_ibs_init(void)
|
||||
{
|
||||
if (!ibs_caps)
|
||||
return -ENODEV; /* ibs not supported by the cpu */
|
||||
|
||||
perf_pmu_register(&perf_ibs, "ibs", -1);
|
||||
perf_ibs_pmu_init(&perf_ibs_fetch, "ibs_fetch");
|
||||
perf_ibs_pmu_init(&perf_ibs_op, "ibs_op");
|
||||
register_nmi_handler(NMI_LOCAL, perf_ibs_nmi_handler, 0, "perf_ibs");
|
||||
printk(KERN_INFO "perf: AMD IBS detected (0x%08x)\n", ibs_caps);
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
Loading…
Reference in New Issue